Technical Program

The VDAT 2005 Tutorials and Symposium will be held during August 10-13, 2005.  The technical program of the events can be navigated here:

Tutorial – I: Analog Design and Synthesis Issues for Scaling CMOS Technologies

Speakers: Dinesh Sharma, IIT Bombay, Chetan Parikh, DA-IICT and Ranga Vemuri, University of Cincinnati

As device dimensions and operating voltages are scaled down, conventional approaches to the design of analog circuits have to be modified. This tutorial will present a review of some major techniques used in analog circuit design for low-voltage applications.  The CMOS amplifier will be the focus of the tutorial, although many of the techniques described will be applicable for a variety of analog circuits.  The topics covered in the tutorial are:

• Brief review of conventional CMOS amplifier design

• Relationship between the transistor parameters and biases, and amplifier performance; basic design techniques.

• Low-power design - Rail-to-rail amplifier architectures, feedback techniques, and current source/mirror architectures.

• Analog Circuit Synthesis – sizing, layout synthesis, topology selection/generation, performance closure

• Overview of synthesis techniques

• Analog performance modeling – macro models and symbolic models

• Layout-inclusive synthesis models – parasitic estimation, layout sampling, convergence and efficiency

The speakers are well known personalities in Analog design and synthesis domain.

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Tutorial – II: Implementation Challenges in Embedded Systems

Speakers – Ajit Rao, TI India, Mani Manoharan, Wipro, Indrajith Radhakrishnan, Wipro, Sadashivan Manickam, Wipro, Pradeep Ganesh Natarajan, Wipro. Coordinator: Arvind Chauhan, Wipro 

This tutorial will discuss the challenges in development of Embedded Systems. The topics covered in the tutorial include:

• Porting Embedded Linux for an ARM based system - Key Kernel elements to be ported, Porting Steps and Debugging, Ensuring Stability and Stress Testing

• USB Software Stack Development for Embedded Systems - USB Software Components, Key System Resource Requirements, USB Stack Implementation for Embedded Linux

• HW/SW Partitioning - Design Decisions, Tools and Techniques

• HW/SW Cosimulation - SoC HW-SW Design Constraints, Need for Cosimulation, Tools and Techniques, Example

The speakers are expert practicing professionals in the area of Embedded Systems. Since the space for tutorials is limited, we may be forced to shortlist participants. If we are unable to register you, you will be intimated by e-mail, and a refund will be made by the VLSI Society of India.

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August 11, 2005 (Thursday) : Day 2

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August 12, 2005 (Friday) : Day 3

 

Advance Program for August 12, 2005 (Friday) - Day-3
9.00 AM - 9.30 AM	Registration
9.30 AM - 10.30 AM	Session 3A-1: Keynote Talk Speaker: Ramesh Emani, Wipro Technologies: Design Going Global: Implications and Lessons Chair: Nagaraj Subramanyam, Texas Instruments Venue: Room-Coral
10.30 AM - 11.00 AM	Tea Break
11.00 AM  - 12.00 PM	Session 3A-2: Keynote Talk Speaker: T.W. Williams, Synopsys Design For Testability – What is it and How did we get here? Chair: C.P. Ravikumar, Texas Instruments, India Venue: Room-Coral
12.00 PM  - 1.00 PM	Session 3A-3 Design Techniques – I Chair: G. S. Visweswaran, IIT Delhi Venue: Room-Coral	Session 3B-3 Low Power – I Chair: Navakanta Bhat, IISc, Bangalore Venue: Room-Mermaid	Session 3C-3 EDA – II Chair: Partha Ray, National Semiconductor Venue: Room-Dolphin
	K.K. Muralidharan, Wipro Technologies Mixed design of Self-Timed Logic in Synchronous Systems Embedded Tutorial	S. Sarkar and Subash Chandar G., Texas Instruments India Low Power Techniques for CMOS Designs Embedded Tutorial	H. Rahaman Bengal Engg. College, D.K. Das, Jadavpur University, and B.B. Bhattacharya, IIT Kharagpur Synthesis and Testing of Reversible Logic – A Survey Embedded Tutorial
	A. Chaudhary, G. Gupta and M. Balakrishnan, IIT Delhi Factoring Large Numbers using FPGA	Siri Uppalapati, GDA Technologies, Inc., USA, Michael L. Bushnell, Rutgers University and V.D. Agrawal, Auburn University Glitch-Free Design of Low Power ASICs using Customized Resistive Feedthrough Cells	S. Mandal, Soumya P., A. Somani, S. Sural and A. Patra IIT Kharagpur UML based Object Oriented Methodology for Analog Test Structure Design Automation
1.00 PM - 2.00 PM	Lunch
2.00 PM - 3.00 PM	Session 3A-4 Low Power – II Chair: P.V. Anandmohan, ECIL Venue: Room-Coral	Session 3B-4 Applications – II Chair: P.R. Panda,  IIT Delhi Venue: Room-Mermaid	Session 3C-4 EDA – III Chair: M. Balakrishnan, IIT Delhi Venue: Room-Dolphin
	A.P. James and Ajayan K.R., College of Engineering, Trivandrum Nanoscale design of Low power Supply Pseudo Resistive Cascode Current Mirror	D. Mukhopadhyay and Dipanwita R.C., IIT Kharagpur Programmable Galois Multiplier Using Cellular Automaton	B. Sarker, Cadence Design Systems Petri Net Modeling of GALS and Implementation in Baseband Datapath component of an IEEE 802.11a compliant modem
	R. Paul, A. Patra and S. Mukhopadhay, IIT Kharagpur Verilog - A Modeling of Parasitic and Biasing effects in PSRR behavior of Brokaw Bandgap Voltage Reference	G.S. Nim, B.S. Chauhan and A. Thapliyal, IRDE, Dehradun Real-Time Image Processing System	A. Sarkar, P.P. Chakrabarti and Rajeev K., IIT Kharagpur Boundary Fair Round-Robin: A Fast Fair Scheduler
	V. Lakshmi Prabha, K. Balamurugan, GCT, Coimbatore and Elwin C.M., Government college of Engineering, Vellore Online Adaptive Power Management for Non-Stationary Service Request	H. Dhand, N.Goel, M.Agarwal and K.Paul, IIT Delhi Partial and Dynamic Reconfiguration in Xilinx FPGAs – A Quantitative Study	S. Chatterjee, P.P. Chakrabarti and Rajeev K., IIT Kharagpur An Optimal Algorithm for Register Renaming: A Post Compilation Technique
3.00 PM - 3.30 PM	Tea Break
3.30 PM – 4.30 PM	Session 3A-5: Keynote Talk Speaker: Kaushik Roy, Purdue University. Advances in Low Power Design Techniques Chair: Bharadwaj Amruthur, Indian Institute of Science Venue: Room-Coral
4.30 PM - 5.30 PM	Session 3A-6: Invited Talk Chair: Vishwani Agrawal, Auburn University Speaker: Nilanjan Mukherjee, Mentor Graphics Corporation, USA. Test Quality Challenges in the Nanometer Era Venue: Room-Coral	Session 3B-6: Invited Talk Chair: Dinesh Sharma, IIT Bombay Speaker: Ashok Balivada, Analog Devices, India. Signal Integrity and Analysis Venue: Room-Mermaid	Session 3C-6: Invited Talk Chair: Shabbir Batterywala, Synopsys Speaker: Susmita Sur-Kolay, Indian Statistical Institute Advances in Physical Design Automation Venue: Room-Dolphin
5.30 PM - 6.00 PM	Break
6.00 PM - 7.00 PM	Session 3A-7 Poster Papers Testing – I Chair: Bhargab Bhattacharya, ISI Calcutta Venue: Room-Coral	Session 3B-7 Poster Papers Synthesis Chair: Anantha Bhat, Synopsys Venue: Room-Mermaid	Session 3C-7 Poster Papers Applications – III Chair: V. Kamakoti, IIT Madras Venue: Room-Dolphin
	S.K. Nathappan, M.V. Raghavulu and Vanathi P.T., PSG College of Technology, Coimbatore CMOS SRAM Fault Detection Using Dynamic Power Supply Current	S. Saha, IIT Roorkee, S. Sarkar and S. Sur-Kolay, Indian Statistical Institute Comparative study of Logic Synthesis Objectives in FPGA Design Flow	M.A. Khan and Y.P. Singh, CDAC, Noida Omura’s Modular Addition for FPGA Implementation of IDEA Cipher Block
	D. Mukhopadhyay and N.N. Mojumder, Jadavpur University Energy-Performance Improvement of Content Addressable Memory by Dual-Threshold CMOS Technology	M.S. Bhat, Rekha S. and H.S. Jamadagni, CEDT, IISc, Bangalore Synthesis of Multiple-Valued Arithmetic Functions using Evolutionary Process	Naveen H.N. and N.Shekar V.Shet, NITK, Surathkal Performance optimized VLSI Implementation of RC5 Encryption Algorithm
	Seema B., Thapar Institute of Engineeing & Technology, Patiala and G.K. Sharma, IT Group, IITM, Gwalior Search Space Pruning for Faster Test Generation based on Parallel and Adaptive GA	A. Bhasin, S. Arora and M. Ameria, HCL Technologies, Noida Enabling ESL Design Through Behavioral Synthesis	S. Anandh, L.Karthick, L. Ponnambalam, S. Rajaram and V.Abhaikumar Thiagarajar College of Engineering, Madhurai FPGA Implementation of OFDM WLAN Modem
7.00 PM – 8.30 PM	Banquet Dinner
End of Day-3

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August 13, 2005 (Saturday) : Day 4

 

Advance Program for August 13, 2005 (Saturday) - Day-4
9.00 AM - 9.30 AM	Registration
9.30 AM - 10.30 AM	Session 4A-1: Keynote Talk Speaker: Sumeet Agarwal, Mobility Group, Intel: Power management Chair: V. Visvanathan, Texas Instruments Venue: Room-Coral
10.30 AM - 11.00 AM	Tea Break
11.00 AM  - 12.00 PM	Session 4A-2 Testing – II Chair: Ram Jonnavithula, Texas Instruments India Venue: Room-Coral	Session 4B-2 Memory Design Chair: Jayanta Lahiri, Alliance Semiconductors Venue: Room-Mermaid	Session 4C-2 Architecture Chair: Ravi Koodli, Infineon Venue: Room-Dolphin
	Thakur S. K., A. N. Chandorkar, IIT Bombay and R.A. Parekhji, TI India Diagnostic Testing of Memories for Static and Dynamic Faults	A.S. Kothari, Purplevision Technologies Area Optimization Tips in Memory BIST	P.R. Panda, IIT Delhi and Viresh Kumar, Infineon A technique for predicting the effect of Data Cache Associativity
	P. Basu, S. Das, A. Banerjee, P. Dasgupta and P.P. Chakrabarti, IIT Kharagpur Test Plan Coverage by Formal Property Verification	A.S. Mudlapur, Vishwani Agrawal, and Adit Singh. Auburn University, A Novel Random Access Scan Flip-Flop Design	C. Karfa, J.S. Reddy, S. Biswas, C.R. Mandal, D. Sarkar, IIT Kharagpur SAST: An Interconnection Aware High-level Synthesis Tool
	S. Banerjee and Dipanwita R.C., IIT Kharagpur An Integrated Computer Aided Test (CAT) Tool for System on Chip	Vasudha G. and Rengarajan K., Texas Instruments India An Accurate Critical Path Based Characterization Scheme for Memory Compilers	S. Bhanja and Thara Rejimon, University of South Florida Probabilistic Error Model for Unreliable Nano-logic Gates
12.00 PM  - 1.00 PM	Session 4A-3 VSI – The Road Ahead Chair: C.P. Ravikumar Venue: Room-Coral	Session 4B-3 Analog Design Chair: Shanti Pavan, IIT Madras Venue: Room-Mermaid	Session 4C-3 DSP Chair: Nitin Chandrachoodan, IIT Madras Venue: Room-Dolphin
	The calendar of VLSI Society of India for 2006 is under construction. Proposals for holding events of VSI are invited.  Brief reports from workshops held in 2005 will be presented by respective organizers. If you wish to hold a workshop on a specific topic, please write to ravikumar@vlsi-india.org. You will be invited to make a brief presentation about the event, including the title of the workshop, its intent, expected outcome, and budget. You can download the appropriate form from http://vlsi-india.org to help you with the planning.	S. Moghe, S. Biswas, J.K. Agrawal, D. Sarkar, S. Mukhopadhyay and A. Patra, IIT Kharagpur A Hybrid System Approach to Failure Diagnosis of Analog VLSI Circuits: A Case Study of DC-DC Buck Converters	N.J.R. Muniraj, Sona College of Technology and R.S.D.Wahida Banu, Government College of Engg, Salem On ways to improve the Adaptive Filter Technique using Verilog HDL and CPLD
		Uday Goel, Sachit Grover and G.S. Visweswaran, IIT Delhi Low Voltage Current Mode Pipelined Analog to Digital Converter	G. Seetharaman, B. Venkataramani and G. Lakshminarayanan, NIT, Tiruchirappalli Design and FPGA Implementation of Wavepipelined Image Block Encoders using 2D-DWT
		K.S.R.K. Prasad, N. Suresh and B. Swapna , N.I.T., Warangal A 1.2V Low Power CMOS Bulk Driven Operational Amplifier	Satyendra K., K.S Ramesh, Anbuselvi J. and S.R. Choudhury, Central Research Laboratory, BEL FPGA Implementation Of Soft Decision Viterbi Decoder
1.00 PM - 2.00 PM	Lunch
2.00 PM - 3.30 PM	Session 4A-4 Verification Chair: Subir Roy, Texas Instruments India Venue: Room-Coral	Session 4B-4 Design Techniques – II Chair: S.K. Nandy, Indian Institute of Science Venue: Room-Mermaid	Session 4C-4 Testing – III Chair: Vishwani Agrawal, Auburn University Venue: Room-Dolphin
	Suchismita R., P. Dasgupta and P.P. Chakrabarti, IIT Kharagpur Bounded Model Checking for Open LTL	M.S. Bhat, Rekha S. and H. S. Jamadagni, CEDT, IISc Bangalore Multi-level Current-mode Signaling for Long High-Speed Interconnects	Sarveswara Tammali and Jais Abraham, Texas Instruments India Testing methods, Parameters and Test sequencing for VLSI Devices Embedded Tutorial
	S. Das, P. Basu, P. Dasgupta and P.P. Chakrabarti, IIT Kharagpur Syntax-driven Approximate Coverage Analysis for an Assertion Suite against a High-level Fault Model	V.B.S. Acharya, S. Kakde, S. Tantry and Koyama Hiroshi, Sanyo LSI Technology Design and Implementation of Class AB CMOS Power Amplifier using GSMC 0.15u Technology	S.K. Sharma, Wipro Technologies Effect of Timing Jitter on High Speed Data Converter System
	K.K. Jha, A. Raychaudhuri, D. Jain, Shubha G., David P., Analog Devices and P. Swaroop, NCSU, USA A 16-bit, 200uA, 10us, Monotonic DAC Converter in SOT-23 package	Presentation by Participants of the Custom LSI Design Workshop 2005 Lessons Learnt from Custom LSI Design Workshop – Project 1 (Coordinator: Mahant Shetti)	Alok S. Doshi and V.D. Agrawal, Auburn University, USA Independence Fault Collapsing
	S. Chattopadhyay, IIT Kharagpur, G. Das and H. Bhoumik, SIT Siliguri Integrated Core and Interconnect Testing with Test-time and Scan Power Minimization	Presentation by Participants of the Custom LSI Design Workshop 2005 Lessons Learnt from Custom LSI Design Workshop – Project 2 (Coordinator: Mahant Shetti)	T.C.S. Reddy, M.V. Raghavulu, P. Kalpana, P.T. Vanathi and K. Gunavathi, PSG College of Technology, Coimbatore On-Line BIST for Testing of Operational Amplifiers
3.30 PM - 4.00 PM	Break
4.00 PM – 6.00 PM	Session 4A-5: Panel Discussion Need of the Hour for the Indian VLSI Industry – Execution or Innovation? Panelists: Mahesh Mehendale, Texas Instruments, Raj Khare, Broadcom, Rajat Gupta, Beecem India, A. Vasudevan, Wipro Moderator: C.P. Ravikumar, Texas Instruments, India Venue: Room-Coral
End of VDAT 2005 Symposium

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