5^th IEEE VLSI Design & Test Workshops

To promote applications and research related to all aspects of VLSI

August 16-18, 2001

JN Tata Auditorium, NSSC Complex, IISc, Bangalore, India

 

Topics of Workshops

The following three workshops will be held concurrently:

·Workshop on High-level Design will discuss issues related to system-level synthesis, core-based design of SOC, timing convergence, high-level synthesis, logic synthesis, and FPGA synthesis.

·Workshop on Physical Design and VLSI Technology will discuss issues related to floor planning, placement, and routing of high-performance integrated circuits.  The workshop will also address issues on the design, modeling and manufacturing issues related to submicron semiconductor and optical technologies.

·Workshop on Testing will discuss issues related to testing and testability of digital, analog, and mixed-signal circuits and systems.

ADDRESS FOR CORRESPONDENCE

C.P. Ravikumar

Controlnet (India) Pvt Ltd.

L-44, Unit-1, Software Technology Park

Verna Industrial Estate, Verna

Salcete, Goa, 403722

Email: ravikumar@controlnet.co.in or

rkumar@ee.iitd.ernet.in

FAX: 91-832-783614.

 
Site was last updated on 11/08/2001.
Comments may kindly be sent to C.P. Ravikumar.