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CALL FOR
PARTICIPATION
5th IEEE VLSI
Design & Test Workshops August 16-18, 2001 Bangalore, India Sponsored by VLSI Society
of India In Cooperation With:
IEEE-CS-TTTC, IEEE CS-VLSI (Confirmation Awaited) Related Site: http://vlsi.ccrl.nj.nec.com |
History:
|
Workshop Title |
Venue |
Date |
Partici-pants |
|
1st VDAT
Workshops |
Chennai |
January 7, 1998 |
30 |
|
2nd VDAT
Workshops |
New Delhi |
August 6-7, 1998 |
70 |
|
3rd VDAT Workshops |
New Delhi |
August 20-21, 1999 |
120 |
|
4th VDAT
Workshops |
New Delhi |
August 25-26, 2000 |
150 |
Topics of Workshops:
The following four workshops will be held concurrently:
Workshop on High-level
Design will discuss issues related to system-level synthesis,
core-based design of SOC, timing convergence, high-level synthesis, logic
synthesis, and FPGA synthesis.
Workshop on Physical
Design will discuss issues related to floor-planning, placement, and
routing of high-performance integrated circuits. The workshop will also
encourage papers related to fabrication and packaging of integrated circuits
and systems.
Workshop on Testing
will discuss issues related to testing and testability of digital, analog, and
mixed-signal circuits and systems.
Workshop on VLSI
Device and Process Technology will discuss design, modeling and
manufacturing issues related to submicron semiconductor and optical
technologies.
The VLSI Education Day (VED
2001) will be held as part of VDAT 2001, on August 16, 2001.
Technical Program Committee
Ø
C.P. Ravikumar, IIT Delhi, General Chair and Test Workshop Coordinator
Ø
Anshul Kumar, IIT Delhi, High-level Design Workshop Coordinator
Ø
Bhargab Bhattacharya, ISI Calcutta, Physical Design Workshop
Coordinator
Ø
Chandrashekhar, CEERI, and G. H. Sarma, ITI, Technology Workshop
Coordinators
Technical Program Committee
Vishwani Agrawal, Bell Labs,
USA
Juergen Becker, Tech. Univ. of Dormstadt, Germany
Bhargab Bhattacharya, ISI Calcutta, India
Chandrashekhar, CEERI Pilani, India
P. Chakrabarti, Banaras Hindu University
P.P. Chakrabarti, IIT Kharagpur, India
Srimat Chakradhar, NEC, USA
Kozo Kinoshita, Osaka Gakuin University, Japan
K.S. Gurumurthy, UVCE, Bangalore, India
Anshul Kumar, IIT Delhi, India
Gopal Mani, CRL, BEL, India
R. Parekhji, Texas Instruments, India
N.S. Murthy, IBM Global Services, India
Dipankar Nagchoudhury, IIT Delhi, India
Shreedhar Natarajan, Texas Instruments
V. Ranganathan, Realchip, India
C.P. Ravikumar, IIT Delhi, India
Vineet Sahula, MREC, Jaipur, India
G.H. Sharma, ITI Bangalore, India
Vinay Shenoy, Philips Semiconductors, India
P. Sridhar, Controlnet, India,
M.N. Sreerangaraju, BIT, Bangalore, India
Susmita Sur-Kolay, ISI Calcutta, India
Alok Singh, Virage Logic, India
ADDRESS FOR CORRESPONDENCE
Authors should submit extended abstracts for talks, proposals for
embedded tutorials (1 hour or 2 hour duration), and proposals for panel
discussions or special sessions, to:
C.P.
Ravikumar
Controlnet
(India) Pvt Ltd.
L-44,
Unit-1, Software Technology Park
Verna
Industrial Estate, Verna
Salcete,
Goa, 403722
Email: ravikumar@controlnet.co.in or
If submitting by email, the author must use either ASCII text, PDF, or postscript format.
IMPORTANT DATES
Last Date for submission: April 30, 2001
Notification of acceptance: June 30, 2001
Last day to received final abstract: August 1, 2001
Workshop Dates: August 16-18, 2001
NOTE: The
workshops are a forum to promote research and development in all aspects of
VLSI in India. Authors will not be asked to submit full papers. Papers
presented in the workshops can be revised and published/presented in other
forums.
