Schedule for Day 1 (Dec 28)

Interconnect RC parameters are significant components of circuit performance, signal integrity and reliability in IC design. Due to manufacturability and reliability issues, the effective dielectric constant of the inter-metal dielectric is not scaling commensurate with the technology scaling predicted in the ITRS roadmap. Metal resistance is also increasing due to electron scattering effects, which exacerbates the interconnect RC scaling issues in sub-100nm technology nodes. The increase in contact and via resistance further aggravates the technology entitlement issues. Although reverse scaling is an attractive option for high performance designs, area entitlement is an issue in routing limited designs. Overall improvement in interconnect performance relies more and more on architecture & design techniques and novel interconnect schemes. The sessions on Day 1 review interconnect scaling, signal integrity, physical design, architecture solutions and optical interconnect.

08.00 AM – 09.00 AM

Registration

09.00 AM – 09.30 AM

Inauguration and opening remarks

SESSION-1

09.30 AM – 10.30 AM

Dr. Shankar Balachandran, IIT Madras, Chennai, India

Pre-placement Estimation and its Applications

Abstract

The topic covers various new ideas in predicting congestion and delay before placement and also touches upon what correlation exist between such estimates and the final implementation, and about the issues in integration of these techniques in the current design flows.

10.30 AM – 11.00 AM

Tea Break

11.00 AM – 12.00 NN

Dr. Ram Achar, Carleton University, USA

Fundamentals and Advances in Modeling/Simulation of High-Speed Interconnects for Signal Integrity Analysis

Abstract

The intense drive for signal integrity has been at the forefront of rapid and new development in CAD algorithms. With increasing demands for high signal speeds coupled with decreasing feature sizes, interconnect effects such as signal delay, distortion and crosstalk become the dominant factors limiting overall performance of high-speed systems. On the other hand, interconnect structures can be diverse and present at any of the hierarchical packaging levels including integrated circuits, printed circuit boards, multi-chip modules and backplanes.

If not considered during the design stage, interconnect effects can cause failed designs. Since extra iterations in the design cycle are costly, accurate prediction of these effects is a necessity in high-speed designs. Although conventional CAD tools such as SPICE are used routinely by many engineers for analog simulation and general circuit analysis, these tools do not handle adequately the new emerging challenges of interconnect effects.

In this talk, an overview of the high-frequency issues and the related modeling/simulation difficulties will be discussed. It will present an overview as well as the most recent advances in the interconnect modeling/simulation   strategies   with   emphasis on distributed multiconductor interconnects and tabulated (scattering) type of subnetworks. Various levels of interconnect modeling will be considered and the applications cover wide spectrum of on-chip, multi-chip, packages, printed circuit boards, backplanes/connectors.

12.00 NN – 01.00 PM

Vijay Sindagi, Texas Instruments, Bangalore, India

How To Use 1000 Processors On A Chip?

Abstract

The era of high performance computing through frequency scaling alone has come to an end. The architecture of wide issue scalar processor designs is yielding diminishing benefits due to the global interconnect in most of it’s structures. Other limiting factors such as cost, reliability and power are requiring increased attention. While this is true of general purpose desktop computing, the challenges facing embedded computing systems are even greater due to their mobility, security and ease-of-use requirements.

Parallel processing as a means to scale performance in both control intensive and data parallel applications has been propounded for 30+ years. It has now become possible to integrate several hundred microprocessors on a single device. But the von Neumann sequential bottleneck and high software inertia are hindering the adoption of large scale parallel processing. Processor implementations are headed towards simultaneous multi-threading and small scale symmetric multi-processing. In this talk we will look into problems due to degrading interconnect and some architectural solutions in the general purpose and embedded computing domains.

01.00 PM – 02.00 PM

Lunch

SESSION-2

02.00 PM – 03.00 PM

Dr. Krishna Saraswat, Stanford University, USA

Performance Limitations of Cu/low-k Interconnects and Possible Alternatives

Abstract

Continuing current scaling paradigm of copper interconnects for signaling, clocking and I/O presents a serious power and performance bottleneck in high-performance integrated circuits (IC). This is further exacerbated by the increase in copper resistivity, as wire dimensions and grain size become comparable to the bulk mean free path of electrons in copper (~40nm) The paradigm shift toward multi-cores would require many longer global interconnects to communicate between cores, thus global wires would have to be pipelined deeper, in turn, latency becomes further worse. Thus, it is imperative to examine alternate interconnect schemes for future ICs. In this work we examine the limits of Cu/low-k interconnects and explore possible advantages of alternative technologies. The three most important novel potential candidates examined are optical and carbon nanotube (CNT)-based interconnects and three-dimensional (3-D) integration.

Our modeling of resistance of diffuse, on chip, RC lines in the light of technological and reliability constraints shows that scaling induced increase in electron surface scattering, fractional cross section area occupied by the high resistivity barrier, and realistic interconnect operation temperature will lead to a significant rise in the effective resistivity of copper. Although, above constraints have been insignificant in the past, they are beginning to effect the interconnect performance and will become increasingly important with the aggressive scaling suggested in the ITRS. We have modeled the impact of the realistic resistance of copper on key interconnect performance metrics, namely, speed and power consumption. The discussion on speed includes interconnect latency with and without optimally inserted repeaters.  Although, repeaters improve speed, they increase power dissipation. With the motivation of reducing this repeater power, an efficient delay-power trade off is developed. Finally, both the repeater device area as well as the chip area penalty because of routing blockage caused by repeaters is addressed. The modeling of repeater penalties at future technology nodes is done in the light of technology dictated, realistic copper resistivity. Where relevant, the results are contrasted with those obtained using ideal copper resistivity.

To get around some of the limitations of conventional metal-based schemes one promising technique is 3-D ICs with multiple active Si layers. A large number of information signals paths could be transferred from horizontal to vertical interconnects. This can potentially increase transistor packing density, reduce chip area, interconnect length and therefore interconnect delay. Our simulations show that vertical integration of devices would allow a substantial reduction in chip size and thus limiting the maximum required interconnect wire length resulting in reduced interconnect delay and power. A brief review of 3-D technologies will be presented.

Another promising technique is optical interconnects. Implementation of optical systems in high performance IC’s can potentially have bandwidth, delay, cross-talk and power advantages. While, the usefulness of optics in chip-to-chip communication is becoming clearer, there exists some ambiguity in its utility in high performance on-chip applications. On-chip optical interconnects can potentially find application for both global signaling as well as clock distribution purpose. We model the optical interconnect system delay, bandwidth and power consumption for global signaling, clocking and I/O. Optical interconnects can potentially reduce latency and provide high-bandwidth with low power dissipation. For off-chip communication, the high local clock frequency (>40Gb/s, using time division multiplexing) can be beneficial for optics. Although for on-chip global wires, the improvement on-chip global clock frequency is leveled off, but it is still be favorable at least for power dissipation and latency Error! Reference source not found. However, an optical waveguide (medium), has a relatively larger size (pitch~0.6µm), making it difficult to provide high bandwidth density, unless on-chip wavelength division multiplexing (WDM) is implemented.

In contrast, CNTs have the flexibility of being implemented in the same size scale as the existing Cu wires, hence possibly can provide high bandwidth density. Single-wall CNT (SWCNT) is very close to one-dimensional quantum wire, whereby electrons move in only one dimension and be scattered only backward, hence the mean free path of electrons for high quality SWCNT is in the micron range. This could result in low latency compared to Cu/low-K counterpart.

03.00 PM – 03.30 PM

Tea Break

03.30 PM – 04.30 PM

Dr. Jaijeet Roychowdhury, University of Minnesota

Photonic Interconnects: Characteristics, Possibilities and Limitations

Abstract

Photonic interconnects have long-term potential to reduce latency, power dissipation, and crosstalk while increasing bandwidth. In this talk, we will present challenges faced by on-chip and chip to chip communications that motivates micro-photonic (optical) interconnects. Critical issues such as system impact of optical interconnects, impact on cache, chip-to-chip communication and global clock distribution will be presented. Finally, practical feasibility issues and limitations related with power, speed, and technology hurdles will be examined. The talk will conclude with some promising recent developments and future outlook of micro-photonic interconnects.

SESSION-3

04.30 PM – 05.30 PM

Panel Discussion

Top 5 Challenges in Interconnect

Moderator: TBA.

Panelists: TBA.

End of Day-1

Schedule for Day 2 (Dec 29)

Design For Manufacturability Yield (DFM&Y) has received much attention in sub-100nm technologies. Addressing the challenges in systematic and random process variations is a critical part of the DFM&Y strategy. Global and local variations in transistors have been analyzed in analog circuits for several years and recently extended to large-scale digital circuits in the form of Statistical Static Timing Analysis (SSTA). In additional to random variations, systematic variations such as stress induced variations need to be considered. In addition to transistor variations, interconnect variations due to Chemical Mechanical Polishing (CMP), etch and process bias are important considerations. Structured layout, variation-aware and variation tolerant design techniques help mitigate variability issues. The sessions on Day 2 review key aspects of lithography, CMP, etch and stress induced variations, SSTA methods and variation tolerant design techniques.

08.00 AM – 09.00 AM

Registration

SESSION-1

09.00 AM – 10.00 AM

Dr. N.S. Nagaraj, Texas Instruments, USA

DFM&Y: Whose problem is it anyway?

10.00 AM – 11.00 AM

Dipu Pramanik, Greg Rollins, Xi-Wei Lin, Xiaopeng Xu and Xiao Lin, Synopsys, Mt View, Ca, USA

Accurate simulation of Electrical and Mechanical Stress Effects in Interconnects for 65nm and below

Abstract

Copper and low k dielectrics are needed to reduce RC delays in 65nm and below logic processes. As line width and pitch for the metal interconnects are scaled down, a wide variety of process related effects impact the performance and reliability of the metallization system. The performance of the circuit is dominated by the capacitance and resistance of the metal lines, which are strongly affected by lithography and CMP. These process steps cause the average line width and thickness of the lines on silicon to be dependent on the layout.  In order to accurately predict performance, Parasitic Extraction tools have to be able to extract accurate values based on the final dimensions on silicon.  Several techniques used by the extraction tools range from accurate 3D field solvers to quasi 2D pattern matching techniques, depending on the size of the circuit. The different techniques are compared as far as accuracy vs speed and it is shown how a flow that integrates these different techniques allows the optimum tradeoff between accuracy and speed. With the right methodology, the flow can also be extended to account for the challenges associated with decreasing feature size. Examples are given of optical simulation of the metal patterns that are coupled with extraction techniques to provide accurate capacitances.  For leading edge technologies, it is also important that the overall extraction methodology account for the distribution of line width and thickness of metal lines as well as that of dielectric thickness, introduced by Process variations. In addition the impact of Mechanical stress needs to be taken into account. The mechanical stress arises as a result of the manufacturing steps and is further enhanced by the package in which the die is placed. Mechanical stress is responsible for cracking of dielectrics as well as formation of voids in metal interconnects leading to both yield and reliability problems. It is shown that while the process and material properties play a major role in the failure rate, the actual layout of the interconnects also contributes significantly to the failures. Hence the design flow will need to include simulations of stress on the final layout. Examples are given of how to optimize electrical performance without degrading the yield and reliability due to mechanical stress. In summary, simulation techniques that analyze the actual layout in conjunction with the manufacturing process will become more important for future technology nodes.

11.00 AM – 11.30 AM

Tea Break

11.30 AM – 12.30 PM

Dr. Sarma Vrudhula, Arizona State Univeristy, USA

Stochastic Analysis of Interconnects and Power Grids in the Presence of Process Variations

Abstract

Variations in the interconnect and power grid geometry of nanoscale integrated circuits translate to variations in their performance. The resulting diminished accuracy in estimates of performance at the design stage can lead to a significant reduction in the parametric yield. Thus, determining an accurate statistical description (e.g. moments, distribution, etc) of the interconnect's response is critical for designers. In the presence of significant variations, device or interconnect model parameters such as wire resistance, capacitance, etc., need to modeled as random variables or spatial random processes. Corner based analysis are not accurate, and simulations based on sampling require long computation times due to the large number of parameters or random variables.

In this talk we describe an efficient method to compute the stochastic response of interconnects and power grids.  We consider variations in the electrical parameters as spatial stochastic processes, accounting for both inter-die and intra-die variations.  The technique models the stochastic response as a mean-square convergent orthogonal polynomial series in the process variables which takes into account the underlying probability distributions of the process variables.  The proposed algorithm has been implemented in a procedure called OPERA.  Results from simulations on a number of design test cases match well with those from the classical Monte Carlo SPICE and from perturbation methods.  Additionally OPERA shows good computational efficiency: speedups of up to 100X have been observed over Monte Carlo SPICE simulations for comparable accuracy.

12.30 PM – 01.30 PM

Lunch Break

SESSION-2

01.30 PM – 02.30 PM

Dr. Mustafa Celik and Dr. Kevin J. Le, , Extreme DA, USA

Variation-aware Timing Analysis and Optimization

Abstract

As process and environment variations become increasingly important, their effects need to be taken care of in all steps of a design flow in order to design products with high parametric yields. In this tutorial, we first identify the sources of process variations and explain their potential effect on circuit timing performance. Then, we give a practical introduction to the variation-aware timing and address how they overcome the limitations of traditional corner-based approach. Variation-aware statistical timing analysis capabilities allow designers to reduce unnecessary pessimism and improve design robustness via sensitivity analysis. Furthermore, statistical analysis tools are useful in detecting potential timing failures due to mismatch, which may be missed by a corner timing analysis with insufficient margins. In the final part, we provide a brief introduction to the variation-aware optimization, which can directly optimize the design in the whole process space without requiring multi-corner optimization and achieve better trade-off between timing, area, and power.

02.30 PM – 03.30 PM

Tejas Jhaveri and Dr. Andrzej Strojwas, Carnegie Mellon University, USA

Recent improvements in IC design & manufacturing using regular design fabrics

Abstract

As we push the limits of optical lithography, to enable classical CMOS scaling, more aggressive resolution enhancement techniques (RETs) to produce circuits with acceptable performance, minimum across chip linewidth variations (ACLV), required process window, and sufficient yield. Although in the past complying with design rules was sufficient to ensure acceptable yields for a design, however, for sub 100nm designs this approach tends to create patterns which cannot be reliably printed for a given optical setup, thus leading to hotspots and systematic yield failures. The recent challenges faced by both the design and process communities calls for a paradigm shift whereby circuits are constructed from a small set of lithography friendly patterns which have previously been extensively characterized and ensured to print reliably.

In this talk, we describe the use of a regular design fabric for defining the underlying silicon geometries of the circuit. Nevertheless, blind application of this methodology to the current ASIC design flow would result in unnecessary area and performance overhead. To overcome the penalties introduced by shape-level regularity we also describe a unique design flow, whereby a given RTL is decomposed in as few Boolean functions (bricks) as possible. It will be shown that with a small set of Boolean functions and careful selection of lithography friendly patterns we can not only mitigate but also eliminate such penalties. We discuss the benefits of using extremely regular designs constructed from a limited set of lithography friendly patterns not only to improve manufacturability but also to relax the pessimistic constraints defined by design rules. Specifically we introduce the basis for the use of “pushed – rules” for logic design as is commonly done for SRAM designs. The key to such shape-level regularity is identifying a set of lithography-friendly patterns, which is getting more challenging in the presence of the complex optical interactions experienced in two-dimensional geometries.

Finally, we will discuss results that demonstrate the successful application of regular design fabrics and yield improvements in a 65nm process. Additionally, we will discuss some results from a low power implementation of an ARM926EJ design using regular design fabrics that exploit this new found manufacturability and predictability of regular circuits, to surpass the performance of arbitrarily built logic.

03.30 PM – 04.00 PM

Tea Break

04.00 PM – 05.00 PM

Dr. Vivek De, Intel, USA

Variation-tolerant logic and memory design in nanoscale CMOS

Abstract

Impacts of variations in device characteristics, induced by Process (P), Voltage (V), Temperature (T) fluctuations and aging, on logic and memory designs in nanoscale CMOS technologies will be discussed. Variation sources and scaling trends will be presented. Several circuit and design techniques for variation control and tolerance will be described, with focus on mitigating variation impacts on performance and energy efficiency of microprocessors.

SESSION-3

05.00 PM – 06.00 PM

Panel Discussion

Top Five Challenges in Variability

Moderator – TBA.

Panelists:

Dr. N.S. Nagaraj, Dr. Dipu Pramanik, Dr. Sarma Vrudhula, Dr. Mustafa Celik, Dr.Kelvin J.Le, Tejas Jhaveri, Dr. Andrzej Strojwas and Dr. Vivek De

End of Workshop