First International Workshop on Interconnect Design and Variability

UPDATED : 13 December 2006
About the Workshop ... Program Schedule ... Registration form
Event report ... Event photographs

Organized by
VSI

http://vlsi-india.org/vsi
VLSI Society of India

In cooperation with

Indian Institute of Science, Bangalore

IEEE Circuits and Systems Society

Bangalore Chapter

http://www.ieee.org

First International Workshop on
Interconnect Design and Variability
December 28-29, 2006, Bangalore, India
Venue: Golden Jubilee Hall, ECE Dept, IISc, Bangalore, India

Scope of the Workshop

Interconnect scaling and variability are two difficult challenges in sub-100nm technology nodes. This workshop aims at addressing the following topics.

1.        Latest advances in interconnect modeling and design innovations to continue performance scaling in sub-100nm technologies:
Ø       Technology scaling trends
Ø       New process realities in sub-100nm technologies
Ø       Alternative interconnect methods
Ø       Interconnect analysis algorithms
Ø       Design and Architecture methods to mitigate RC scaling

2.        In depth review of the latest advances in variability in sub-100nm technologies:
Ø       Device and interconnect process variations
Ø       Algorithms related to statistical analysis of performance and leakage
Ø       Practical approaches to address variability
Ø       Variation tolerant design methods

General Co-Chairs:
Nagaraj, N.S. Texas Instruments (Dallas)
C.P. Ravikumar, Texas Instruments (Bangalore)

Program Committee:

v      Andrzej Strojwas, Carnegie Mellon University, USA
v      Dipu Pramanik, Synopsys, USA
v      Jaijeet Roychowdhury, Univ. of Minnesota, USA
v      Krishna Saraswat, Stanford University, USA
v      Larry Pileggi, Carenegie Mellon University, USA
v      Nickhil Jakatdar, Cadence Design Systems, USA
v      Poras Balsara, Univ. of Texas at Dallas, USA
v      Ram Achar, Carleton University, Canada
v      Sachin Sapatnekar, Univ. of Minnesota, USA
v      Yervant Zorian, Virage Logic, USA

Speakers:

.        Dr. Jaijeet Roychowdhury, University of Minnesota, USA
.        Dr. Krishna Saraswat, Stanford University, USA
.        Dr. Ram Achar, Carleton University, Canada
.        Dr. Shankar Balachandran, IIT Madras, Chennai, India
.        Vijay Sindagi, Texas Instruments, India
.        Dr. Andrzej Strojwas, Carnegie Mellon University, USA
.        Dr. Dipu Pramanik, Synopsys, USA
.        Dr. Mustafa Celik, Extreme DA, USA
.        Dr. Nickhil Jakatdar, Cadence Design Systems, USA
.        Dr. Sarma Vrudhula, Arizona State Univeristy, USA
.        Dr. Vivek De, Intel, USA

Course Fee	Before November 28, 2006	After November 28, 2006
Professionals (Non-members)	Rs. 4,000	Rs. 4,500
Professionals (VSI/ IEEE members)	Rs. 3,000	Rs. 3,500
Students/Faculty (Non-members)	Rs. 2,500	Rs. 3,000
Students/Faculty (VSI/ IEEE members)	Rs. 2,000	Rs. 2,500
Download Announcement PDF You must also register using the online registration form at http://vlsi-india.org/vsi/activities/reg.shtml apart from sending the filled hardcopy of registration form to let us know your payment details beforehand.