UPDATED: 3 January 2007
About the Workshop ... Program ... Speaker details ... Registration Form
Panel Discussions on ESL in Education, and ESLD: Opportunities in India were held during the workshop.
Visit for details and to download slides presented. - A brief report - Photographs

Electronic System Level Design Workshop 2007

January 11 -12, 2007

Venue: Wipro Learning Center, Electronics City, Bangalore

About the Invited Speakers

Nikil Dutt received the BE (Hons) degree from BITS, Pilani, MS from Penn State and PhD from the University of Illinois at Urbana-Champaign, and is currently a Professor of CS and EECS at the University of California, Irvine. His research interests are in embedded systems design automation, computer architecture, optimizing compilers, system specification techniques, and distributed embedded systems. He has received numerous best paper awards and is coauthor of 5 books and over 200 journal and conference publications. Professor Dutt currently serves as Editor-in-Chief of ACM ransactions on Design Automation of Electronic Systems (TODAES) and as Associate Editor of ACM Transactions on Embedded Computer Systems (TECS). He was an ACM SIGDA Distinguished Lecturer during 2001-2002, and an IEEE Computer Society Distinguished Visitor for 2003-2005. He has served on the steering, organizing, and program committees of several premier CAD and Embedded System Design conferences and workshops, and serves on the advisory boards of ACM SIGBED and ACM SIGDA.

Rishiyur S. Nikhil is a co-founder and CTO of Bluespec, Inc., which develops chip design tools that dramatically improve correctness and productivity. From 2000 to 2003, he led a team inside Sandburst Corp. (now part of Broadcom) developing Bluespec technology and contributed to 10Gb/s network chip designs. From 1991 to 2000 he was at Cambridge Research Laboratory (DEC/Compaq), including over a year as Acting Director. From 1984 to 1991 he was a professor of Computer Science and Engineering at MIT. He has led research teams, published widely, and holds several patents in functional programming, dataflow and multithreaded architectures, parallel processing, compiling, and EDA. He is a member of ACM, IEEE, and IFIP WG 2.8 on Functional Programming. He received his Ph.D. and M.S.E.E. in Computer and Information Sciences from the Univ. of Pennsylvania, and his B.Tech in EE from IIT Kanpur.

Dr. Sachin Ghanekar
* Completed B.Tech M.Tech, IIT Bombay in '89 from EE Department.
* Worked on "Effient Designs for digital filter architectures using periodically time-varying systems." as a Ph.D. Thesis from University of Massachusetts.
* Since 1993, working in various capacities in the field of Audio Video & communication firmware development.
* Recently, joined Tensilica as a Senior DSP manager to support Tensilica's efforts in designing and extending its configureable cores for addressing audio and video markets.

Charlie Hauck who is VP engineering at Bluespec, has more than 25 years experience in research and development, engineering, marketing and management from within the semiconductor industry. Most recently, he was USA General Manager for Faraday Technology, a fabless ASIC vendor and silicon intellectual property (SIP) provider. From 1998-2003, he served as Vice President of Engineering at Lexra Inc., a microprocessor SIP company. From 1994 to 1998, Hauck was director of application specific integrated circuit (ASIC) development at LSI Logic, responsible for advanced ASIC technology and library development. From 1987 to 1994, he was Director of IC Development at Kendall Square Research, managing the very large scale integration (VLSI) design team responsible for delivering working silicon for its custom chips. Hauck began his career at Commodore, where he completed several VLSI chips and boards for consumer electronics and DSP systems.
Hauck holds a BSEE from the Johns Hopkins University and a MSEE from MIT.

Brian Bailey - Chief Technologist at Poseidon Design Systems Prior to joining Poseidon, Mr. Bailey was an independent industry and management consultant, having worked with a number of startup companies to help them turn their conceptual ideas into practical realities. Prior to that, he was the Chief Technologist for functional verification at Mentor Graphics.
Brian Bailey is the Chairman of the Accellera Interfaces committee and a renowned industry veteran. He contributed to the introduction of RTL simulation, emulation, mixed abstraction simulation, hardware / software co-simulation and transaction level modeling. During 2005, he published two books on the subjects of design and verification and has published many papers and articles over the past several years. He is actively sought out to appear in panels and conferences. He has two patents to his name with others pending and is proclaimed to be one of the visionaries in the emerging ESL field. He graduated from Brunel University in England with a 1st class honours degree in Electrical and Electronic Engineering.

Srinivasan Venkataramanan is currently employed as a Corporate Application Engineer (CAE) Manager with Synopsys, India Private Ltd., Bangalore - India. His areas of interest are the emerging verification solutions and methodologies such as SystemVerilog, VMM, Assertion-Based Verification, formal verification etc. He provides support to leading edge semiconductor design companies on their verification methodologies and challenges. In his previous employment with various design houses, he was actively involved in the verification of leading edge high-speed, multi-million gates ASIC designs. Srini holds a Masters Degree from the prestigious Indian Institute of Technology (IIT), Delhi in VLSI Design, and Bachelors degree in Electrical engineering from TCE, Madurai. Srini has co-authored the following books:
A Pragmatic Approach to VMM Adoption

Using PSL/Sugar for Formal and Dynamic Verification, 2nd Edition

SystemVerilog Assertions Handbook

Amit Sharma has around 5 years of experience in various facets of functional verification of networking chips and protocol, microprocessors and system level platforms. During the last few years, he has been primarily involved in testbench and simulation technologies and the deployment of the same across various designs. He is an EE graduate from REC, Surathkal and is currently working as Lead Verification Solutions Engineer with Synopsys India.

Desingh Balasubramanian is currently a Senior Member Technical Staff in the system level simulation and modeling team of Poseidon Design Systems. His areas of interest include computer architecture, Media processor architectures, system level modeling for design space exploration and design methods for efficient HW/SW co-design. He is a post-graduate degree (MTD) in Embedded Systems from National University of Singapore & Technical University of Eindhoven. He received his B.Tech in Electronics from Madras Institute of Technology, Chennai.

Aravinda Thimmapuram has 8 years of experience in EDA and ESL domains, and is currently with NXP Semiconductors India, Bangalore.

T.S. Rajesh Kumar has 13 yeas of experience at Texas Instruments, India. He has lead various teams at Texas Instruments and has extensive experience in DSP Architectures, Broadband and Wireless System on Chips. Rajesh holds a Bachelor of Engineering degree from Madras University and is currently pursuing his Ph.D at Indian Institute of Science, Bangalore in the area of memory architecture exploration for embedded System on Chips.

Addressing Battery Gap: System-level Techniques for Low-Power Design

Kanishka Lahiri, NEC Labs

Rapidly escalating energy requirements of the electronics contained within mobile devices are quickly outpacing the capacities of the batteries that power them. There is consensus that this emerging "battery-gap" cannot be effectively addressed through low-level (e.g. circuit-level) techniques alone. This has led to increased emphasis on solutions that can be applied earlier in the design cycle, at higher levels of abstraction (e.g., system-level), when significant opportunities exist for optimizing the application and/or architecture for energy efficiency. As a step towards bridging this gap, at NEC Laboratories, we have been focusing on developing technologies for analyzing SoC power consumption at the system-level of abstraction.

This talk describes innovative aspects of our power analysis framework, which includes methods to automatically generate IP power models, and techniques for fast and accurate simulation based power analysis. It will highlight new techniques that we use for achieving high power estimation efficiency, namely, adaptive power modeling, and hardware acceleration using logic emulation platforms. In the second part of this talk, we will discuss techniques targeted towards improving battery-life (as opposed to merely reducing average power consumption), including battery life estimation techniques, a measurement study conducted to analyze the battery-efficiency of commercial wireless sensor nodes, and novel techniques for battery aware power management.

Kanishka Lahiri received his B.Tech degree (1998) in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur, and the M.S. (2000) and Ph.D (2003) degrees in Computer Engineering from the University of California, San Diego.

Dr Lahiri has been affiliated with NEC Laboratories America, Princeton, NJ since 2003; where as Research Staff Member he has contributed to various projects on SoC architectures and design methodologies, with a focus on on-chip communication architectures, and system-level power estimation techniques. He holds (or has filed for) 5 US patents on related topics, has co-authored over 30 papers in leading conferences and journals. He was the recipient of a Best Paper Award and a Best of Practice citation at the IEEE/ACM Design Automation Conference in 2000 and 2002 respectively, and a Special Services Award at the IEEE VLSI Test Symposium in 2003. He program committee assignments include the Intl. Symposium on Low Power Electronic Design (ISLPED'05,'06), the Embedded Systems for Real-time Multimedia Workshop (ESTImedia'06), and the Embedded Systems Codesign Workshop (2002). He is a member of the IEEE.

TUTORIAL I : SYSTEM LEVEL TECHNIQUES FOR POWER OPTIMIZATION

Sandeep K. Shukla, Virginia Tech

In the changing world of pervasive and ubiquitous computing, extensive use of hand held devices, and biomedical devices, embedded computing is becoming increasingly complex. However, complex functionality must not come at the price of reduced battery life for such devices. As a result, power optimization and low-power design of such devices and systems is extremely important. Power optimization goals can be pursued at various levels of design abstraction, such as gate level, micro-architectural level, architecture level, protocol level, system level and at the embedded software level. In this tutorial, the focus is mostly on system level power management.

Dynamic Power Management (DPM) is one form of system level power management. It entails employing strategies that yield acceptable trade-off between power/energy usage and corresponding performance penalties. These include heuristic shutdown policies, prediction based shutdown policies, multiple voltage scaling and stochastic modeling based policy optimization. DPM strategies got increasingly sophisticated due to improved power manageability of hardware components. In this context, there is a positive feedback in action. Power management techniques show the potential for power savings, and this pushes hardware developers to support more advanced (finer grained and lower overhead) power management modes. In this tutorial, we will provide an over view of the main issues namely, architecture level, and system level techniques of power minimization and management, how they influence each other. However, we will not concentrate on low power VLSI techniques.

The target audience for this tutorial comprises of researchers, graduate students and industrial engineers working in the area of low power design, power management, embedded software and hardware design. No prior knowledge of the field will be assumed, other than understanding of algorithmic methods, system design and standard probability theory, and calculus.

In particular, power management approaches that we will discuss rely on formal techniques for the evaluation of the effectiveness of DPM algorithms. For deterministic models of the system, competitive analysis along with learning techniques provide a reasonable framework for their analysis. Stochastic optimization approaches to DPM can be analyzed using advances in probabilistic model checking techniques.

About the speaker
Sandeep Shukla is currently an Assistant Professor of computer engineering with the Virginia Polytechnic and State University (Virginia Tech), Blacksburg. He is also a founder and Deputy Director of the Center for Embedded Systems for Critical Applications (CESCA) and Director of the FERMAT Laboratory, Virginia Tech. He was also elected as a College of Engineering Faculty Fellow at the Virginia Polytechnic and State University. He has authored or couathored over 100 papers in journals, books, and conference proceedings. He coauthored SystemC Kernel Extensions for Heterogeneous Modeling (Kluwer, 2004) and coedited Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation (Kluwer, 2004) and Formal Methods and Models for System Design: A System Level Perspective (Kluwer, 2004). His research particularly focuses on system-level design languages, formal methods, formal specification languages, probabilistic modeling and model checking, dynamic power management, application of stochastic models and model analysis tools for fault-tolerant system design, and reliability measurement of fault-tolerant systems.

Dr. Shukla was the recipient of the National Science Foundation PECASE (Presidential Early Career Award from the White House) Award for his research in design automation for embedded systems design. He has edited a number of special issues for various journals and is on the Editorial Board of IEEE Design and Test, and IEEE Transactions on Industrial Informatics. Sandeep has chaired a number of international conferences and workshops.