Electronic System Level Design Workshop 2007 January 11 -12, 2007 Venue:  Wipro Learning Center, Electronics City, Bangalore

ADVANCE PROGRAM AS ON 08-01-2007
Day 1 – Thursday - January 11, 2007
08.00 AM	Registration and breakfast
09.00 AM	Inauguration Venue – Room Columbus, Wipro Learning Center
	Session 1-A : Keynote Talks Zafar Ahmed K, Senior Design Engineer, ARM Embedded Technologies Pvt. Ltd, India Operation RealView Tools by ARM (ARM Technical Forum, RealView® CREATE SERIES of ESL Tools)   Nikil Dutt, Center for Embedded Computer System, UC Irvine In Search of the Elusive Golden Reference Model for ESLD   A critical challenge in Electronic System Level Design (ESLD) is the lack of a golden reference model that can be used across different facets of ESLD, including design specification, HW/SW co-design, co-validation, and downstream CAD flows.  Indeed, for the task of validation alone, traditional techniques typically employ different reference models depending on the abstraction level and verification task (e.g., functional simulation or property checking), resulting in potential inconsistencies between these multiple reference models.  The problem is further aggravated due to the plethora of different models – generated both automatically and manually – that are used for the tasks of synthesis, simulation, interface generation, estimation, etc. Many open questions remain.  How can we manage consistency between these models? Can all of these models be generated from, or linked to a “Golden Reference” model?  Is the search for a “Golden Reference” model akin to the search for the proverbial “Goose That Laid the Golden Egg”?   This talk will discuss challenges in these domains, and present some possible directions in the context of ESLD for heterogeneous Multiprocessor Systems-on-Chip (MPSOCs).
10.30 AM	Tea
11.00 AM	Session-1B Venue – Room Coral, Wipro Learning Center	Session-1C Venue – Room Columbus, Wipro Learning Center
	Dr. Sachin Ghanekar, Tensilica Designing a DSP core for audio applications using a Configurable Processor	Dr. Rishiyur Nikhil, CTO, Bluespec Inc. Design by refinement  - An ESL technique that starts from an executable specification and successively refines the design to implementation
12.00 PM	Kanishka Lahiri, NEC-Labs Addressing the Battery Gap: System-level Techniques for Low Power SoC  Design	Charlie Hauck, VP Engineering, Bluespec Inc. Automated Fine Grain Low Power Design Techniques
01.00 PM	Lunch
02.00 PM	Session – 1D : Tutorial I Venue – Room Coral, Wipro Learning Center	Session -1E : Tutorial II Venue – Room Columbus, Wipro Learning Center
	Sandeep Shukla, Virginia Tech University System-level Techniques for Power Optimization	Srinivasan Venkataramanan, Synopsys India Improving Verification Productivity using SystemVerilog
04.15 PM	Tea
04.45 PM	Tutorial Continues	Tutorial Continues
06.00 PM	End of Day 1

 

ADVANCE PROGRAM AS ON 08-01-2007
Day 2 – Friday - January 12, 2007
08.00 AM	Registration and breakfast
09.00 AM	Session 2A – Keynote Talk Brian Bailey, Poseidon Design Systems Venue – Room Columbus, Wipro Learning Center
10:00 AM	Tea
10.30 AM	Session 2B - Launching of System C User Group India Chapter Inauguration by members of System C User Group Venue – Room Columbus, Wipro Learning Center
11:15 AM	Session-2C : Tutorial III Venue – Room Coral, Wipro Learning Center	Session -2D: Tutorial IV Venue – Room Columbus, Wipro Learning Center
	Tutorial on ESL Design  Speaker: Brian Bailey, Poseidon Design Systems	System C Tutorial Desingh Balasubramanian, Poseidon Design Systems and Karthick Gururaj, NXP Semiconductors
01.30 PM	Lunch
02.30 PM	Session 2E: ESL in Education Venue – Room Coral, Wipro Learning Center	Session 2F : Industrial Practices Venue – Room Columbus, Wipro Learning Center
	ESL in Education  - Panel Discussion Experts from the industry and academia will discuss the topic of including ESL topics in EE/CS curriculum	T.S. Rajesh Kumar, C.P.Ravikumar, Texas Instruments India and R.Govindarajan, SERC, IISc, Bangalore Memory Optimizations and Exploration for Embedded SoC
	Participants – S. Karthik, Analog Devices, K. Krishna Moorthy, National Semiconductors, S.K. Nandy, Indian Institute of Science. Moderator: Gulur Nagendra, Texas Instruments.	Aravinda Thimmapura, Philips Semiconductors. Performance Analysis of Memory Sub-systems Using Virtual Prototype
04.00 PM	Tea
04.30 PM	Panel Discussion: ESLD in India: Opportunities and challenges Venue – Room Columbus, Wipro Learning Center The panelists will discuss how ESLD may change the landscape of EDA and VLSI Design in India. Moderator: Shiv Tasker, CEO, Bluespec Inc., Panel Members:  Ramesh Subbarao, Texas Instruments; Mudit Mathur, Wipro Technologies, Vishal Suresh, NXP Semiconductor; Vinod Malhotra, Poseidon Systems; S.K. Nandy, Indian Institute of Science
06.00 PM	End of Workshop