UPDATED : 7 August 2007
Course content ... Course details
Download Program Schedule PDF 218KB
Announcement with registration form PDF 144KB

Note: No more new/ spot Registrations for the event are accepted.

Short Course on
Digital Circuits Test and Design For Test

August 13-17, 2007, NOIDA, India

Venue: The Stellar Gymkhana, R-1, Knowledge Park II, Greater Noida, UP - Phone: 91-9811559117 - Website: www.stellargym.co.in

1. Introduction			6. Logic BIST
2. CAD tools			7. Memory Test
3. Logic Test - Typical Fault Models			8. Test Compression
4. Advanced Faults Models			9. Fault diagnosis
5. Design for Test			10. Industrial Case Studies
1. Introduction 1.       Defects in DSM circuits 2.       Systematic, Parametric vs. Random Defects 3.       Yield and quality requirements 4.       Objectives of digital testing 5.       Relationship between defect coverage and DPM 6.       Quality of test versus yield 7.       Different phases and components of test 8.       Factors affecting test		5. Design for Test 1.       Scan designs – a mux-D based scan cell 2.       How scan works? 3.       DRC rule checks – uncontrollable clocks, etc. 4.       Scan and its benefits 5.       Enhanced scan architecture for at-speed tests 6.       Scan-enable signal, pipelined scan-enable signal for at-speed test 7.       Slow shift/fast capture 8.       Enhanced scan architectures 9.       Power conscious test techniques, test architectures
2. CAD tools 1.       Logic simulators 2.       Fault simulators 3.       Test pattern generators 4.       Scan insertion tools 5.       Logic BIST 6.       Memory BIST 7.       Cost of test and test data compression
3. Logic Test - Typical Fault Models 1.       Relation between defects and fault models 2.       Measures – fault coverage, test coverage, test efficiency, etc. 3.       Stuck-at Fault Model 4.       Test pattern generation/fault simulation 5.       Static and dynamic compaction 6.       Delay fault models – transition, path-delay and inline resistance fault models 7.       Launch off shift versus launch off capture 8.       Transistor stuck-open faults, Transistor stuck-on faults 9.       Industrial experience with at-speed tests 10.   Iddq test sets 11.   Effectiveness of Iddq tests on nanometer designs		6. Logic BIST 1.       Requirements for implementing BIST 2.       Pattern Generation - Linear Feedback Shift Register 3.       Characteristics of pseudo-random patterns 4.       Output Compaction – Multiple Input Signature Register 5.       Aliasing probability 6.       Creating a BIST ready design 7.       Handling of X-states 8.       Handling of buses with multiple drivers 9.       Feedback loops, latches 10.   Random Pattern Resistant Faults 11.   Test Points – improve controllability and observability 12.   Overall Logic BIST Architecture 13.   Boundary scan and BIST 14.   A typical BIST session 15.   Fault simulation and signature calculation 16.   ATPG supplement patterns 17.   Logic BIST diagnosis flow 18.   Direct diagnosis from MISR signatures
4. Advanced Faults Models Section A: 1.       Bridging Faults 2.       Targeting Bridging Faults – n-detect test sets 3.       Test Generation for Bridging Faults 4.       At-speed test application 5.       False and multi-cycle paths 6.       Avoiding hold-time violations during ATPG 7.       Timing-aware ATPG 8.       Propagation delay fault model 9.       Validating data hold times 10.   Test pattern ordering Section B: 11.   Power dissipation in scan based test 12.   Power reduction – hardware based approaches 13.   Software based methods – Weighted Switching Activity (WSA) 14.   Capture cycle switching reduction 15.   Reducing switching activity for scan load/unload 16.   Results for industrial circuits
7. Memory Test 1.       Different fault models for memories 2.       Conventional memory test algorithms 3.       Advanced memory test algorithms ·          Address decoder open tests ·          Byte write-enable mask tests ·          Multi-port memory tests 4.       Memory test techniques ·          Direct Access ·          Memory BIST ·          Macro Test 5.       Typical Memory BIST Architecture 6.       Methods for output evaluation 7.       Typical address generators 8.       Memory BIST collar 9.       At-speed test application 10.   Shared controllers – different test configurations 11.   Memory diagnosis 12.   Memory repair for yield improvement 13.   E-fuse based memory repair 14.   Memory BIST through JTAG interface 15.   Localized address/data generation 16.   Programmability – algorithm specification, selection 17.   Field Programmable memory BIST 18.   Macro Test – test small memories via scan vectors 19.   At-speed test application using Macro Test		9. Fault diagnosis Section A: 1.       Detection vs. Diagnosis; goals of diagnosing chip failures 2.       Diagnosis at different levels – chip, board, system 3.       Scan chain diagnosis 4.       Logic diagnosis – methods 5.       Fault dictionaries ·          Effect-Cause or Simulation Based Methods 6.       Diagnostic resolution 7.       Logic diagnosis procedures 8.       Effect of compression on diagnosis 9.       Direct diagnosis algorithms 10.   Industrial case studies for diagnosis Section B: 11.   Current motivations for DFT and test 12.   Design, test, and diagnosis flow 13.   Current methods for yield learning 14.   Defect based testing 15.   Fault models based on physical data 16.   Mapping from logical faults to physical defects 17.   Closing the yield learning loop
8. Test Compression 1.       Conventional scan test – how does it work? 2.       ATE costs for scan vector application 3.       Test costs – data volume and scan test application time 4.       Scalability of scan based solution with increasing design complexity 5.       Requirements for a good compression scheme 6.       Conventional scan and ATPG process 7.       Scope for data volume reduction during ATPG 8.       Non-embedded forms of compression 9.       State of the art decompression techniques 10.   Stimuli repetition, stimuli conversion, and stimuli replication 11.   Stimuli encoding 12.   Reseeding of LFSRs 13.   Continuous Flow Decompression 14.   Ring generators 15.   Encoding capacity 16.   Embedded Deterministic Test (EDT) Architecture 17.   Advantages of using EDT - example 18.   Test response compaction – requirements? 19.   Time and Space compaction 20.   State of the art compaction techniques 21.   Selective compactor 22.   Handling of X-states and aliasing 23.   Finite memory compactors - convolutional and block compactors 24.   Advanced compression techniques – how one can achieve very high compression? 25.   Power reduction in compression based methods 26.   Modular EDT architecture 27.   Burn-in test requirements		10. Industrial Case Studies 1.       SOC Design/test use 2.       SOC test methodology and flow 3.       Test re-use 4.       IEEE 1500 and how it facilitates test reuse 5.       Others…

 

August 13, 14 and 16 Dr. Nilanjan Mukherjee and Prof. Sudhakar M. Reddy v       Introduction v       CAD Tools v       Logic Test – Basics v       Logic Test v       Advanced Fault Models v       Power Aware Test v       DFT v       Logic BIST v       Memory Test v       Test Compression v       Fault Diagnosis

August 17 Dr. C.P.Ravikumar Industrial Experiences v       Process Variation v       Variability Issues in Test v       Power-aware Test Generation v       From DFT to DFTMY

Download announcement with registration form PDF 144KB The registration fee includes registration material, softcopy of notes, lunch and refreshments. Mode of Payment: Demand Draft, drawn in favor of  “VLSI Society of India” payable at Bangalore. Please also register using the online registration form at http://vlsi-india.org/vsi/activities/reg.shtml apart from sending the filled hardcopy of registration form. Spot-registration subject to availability at the after deadline rates against DD or Cash.