UPDATED : 7 August 2007
Course content ... Course details
Download Program Schedule PDF 218KB
Announcement with registration form PDF 144KB

Note: No more new/ spot Registrations for the event are accepted.

Organized by http://vlsi-india.org/vsi VLSI Society of India	Short Course on Digital Circuits Test and Design For Test August 13-17, 2007, NOIDA, India Venue: The Stellar Gymkhana R-1, Knowledge Park II, Greater Noida, UP - Phone: 91-9811559117 - Website: www.stellargym.co.in
The course runs for 4 days, Aug 13-14 and 16-17. Aug 15 is observed as a holiday.
	Summary: Testing of every manufactured device is necessary to ensure product quality. As the complexity of electronic integrated circuits grows, their testing has also become very complex and expensive. This course will provide an overview of the recent trends in testing of digital circuits and designing these circuits for better testability.   Targeted Audience: Targeted audience is practicing engineers, students and academics.   Course conducted by: Dr. Nilanjan Mukherjee, Mentor Graphics Corporation, US; Prof. Sudhakar M. Reddy, Iowa University, and Dr. C.P. Ravikumar, Texas Instruments India   Nilanjan Mukherjee recieved a B.Tech.(Hons) degree in Electronics and Electrical Communications Engineering from IIT Kharagpur, India, and a Ph.D. degree in Computer Engineering from McGill University, Montreal, Canada. He has been with Mentor Graphics since 1999 and is currently leading the Test Synthesis Group in the DFT division. He is a co-inventor of the Embedded Deterministic Test Technology and was a lead developer for TestKompress, the leading test compression tool in the industry. Prior to Mentor, he was with Bell Laboratories at Lucent Technologies.  Nilanjan has published over 40 technical papers at various international conferences and refereed journals. He is a co-author of the paper on "Embedded Deterministic Test" in IEEE Transactions on CAD that won the Donald O. Pederson award in 2006. In addition, his paper on the same topic at ITC 2002 has been recognized as one of the most significant papers in the past 35 years of ITC. He recieved the Best Paper Award at the VLSI Test Symposium in 1995 and co-authored a paper that recieved the Best Student Paper award at the 2001 Asian Test Symposium. Nilanjan is a co-inventor of 13 US patents.  Nilanjan has presented numerous tutorials and seminars at major conferences like ITC, DAC, and VLSI Design, as well as at various Mentor Graphics events in US and India. He is teh General Chair for the 2008 International Test Synthesis Workshop and has been in the Program Committee of numerous conferences such as ITSW, VLSI Design, ATS, DDECS, and VDAT. Professor Sudhakar M. Reddy received the B.Sc. degree in Physics and the B.E. degree in Electronic Communications Engineering (ECE) from Osmania University, Hyderabad, the M.E. degree in ECE from the Indian Institute of Science, Bangalore, India, and the Ph.D. degree from the University of Iowa, Iowa City, Iowa. He joined the faculty of the Department of Electrical and Computer Engineering at the University of Iowa in 1968 where he is currently a University of Iowa Foundation Distinguished Professor of ECE. He served as the Chairperson of the ECE Department from 1981 to 2000. Professor Reddy has published well over four hundred papers in archival journals and the proceedings of international conferences. Several papers co-authored by him received best paper nominations and awards. Professor Reddy has given keynote talks at international conferences. He has also given one-day tutorials to practicing engineers at international conferences. He received a Von Humboldt Prize in 1995 and the first Life Time Achievement Award from the International Conference on VLSI Design. Professor Reddy is a Life Fellow of IEEE. Professor Reddy has served on the committees of several international conferences. He was the Technical Program Committee Chair of the 1989 Fault Tolerant Computing Symposium. He has served twice as a guest editor for the special issues on Fault Tolerant Computing and as an associate editor of the IEEE Transactions on Computers and has been serving as an associate editor of the IEEE Transactions on CAD for the last ten years. Dr. C.P. Ravikumar is with Texas Instruments India as a Senior Technologist in VLSI Test. Before joining TI, he served on the faculty of the Department of Electrical Engineering at IIT Delhi as a Professor. He has published over 150 papers in international conferences and journals. He has served as the technical program chair for VLSI Design Conference and the VLSI Design and Test Symposium. He has also served as the member of the program committee for several conferences, including HiPC (High Performance Computing). He is the recipient of SIGDA student scholarship award, best paper award (VLSI Design conference) and best student paper award (VLSI Design conference). He is a senior member of IEEE, Fellow of the Indian Microelectronics Society, and current secretary of VSI.
Registration Fee Before July 13, 2007 After July 13, 2007 Professionals (Non- Members) Rs.8,000/- Professionals (Non- Members) Rs.9,000/- Professionals (VSI/ IEEE members) Rs.7,000/- Professionals (VSI/ IEEE members) Rs.8,000/- Students/Faculty  (Non-members) Rs.6,000/- Students/Faculty  (Non-members) Rs.7,000/- Students/Faculty  (Members of VSI/ IEEE) Rs.5,000/- Students/Faculty  (Members of VSI/ IEEE) Rs.6,000/-
Download announcement with registration form PDF 144KB The registration fee includes registration material, softcopy of notes, lunch and refreshments. Mode of Payment: Demand Draft, drawn in favor of  “VLSI Society of India” payable at Bangalore. Please also register using the online registration form at http://vlsi-india.org/vsi/activities/reg.shtml apart from sending the filled hardcopy of registration form. Spot-registration subject to availability at the after deadline rates against DD or Cash.

 

Venue   The Stellar Gymkhana is adjacent to the Noida Expressway connecting the Amity School in Noida to Pari Chowk in Greater Noida. It is about 20 minutes drive from Noida and 40 minutes from South Delhi. It takes about 1-1/2 hours from the international airport, 1 hour from Domestic Airport and approx 1 hour from New Delhi Railway Station. Other details related to location can be found on http://www.stellargym.co.in/location.html   Conveyance   The Stellar Gymkhana is located on the Noida express highway, and approximate taxi charges are per 8hr / 80km concept and the cost would be normally around 1000/- from both airport and station. Generally cabs charge on garage-to-garage basis. More information on the prepaid taxi or Easy cabs can be obtained from www.carzonrent.com   Accommodation   Participants are to make their own stay arrangements. Below are a few links and details of Hotels at Noida:   The Stellar Gymkhana R-1, Knowledge Park II, Greater Noida, UP Phone: 91-9811559117 (Contact Ms.Sheetal Goel) Website: www.stellargym.co.in   Hotel Rama www.hotelrama.net   Rai Residency B-203, Sector-19, Noida Ph: 0120-2544952, 2547503 Mobile: 9811722103 (Contact: Mr. B.K.Verma)