Day-1: August 26,
2004 (5.30
PM – 6.30 PM)
|
Session
D1-Poster-1
FPGA
Applications
Venue – Subhash
Chandra Bose
|
Session
D1-Poster-2
Logic Design
Venue – Room
Bhagat Singh |
Session
D1-Poster-3
Systems Design
Venue – Room Chanakya
|
|
Electronic Flow
Regulator (EFR) Using Field Programmable Gate Arrays (FPGA)
J.Manikandan,
M.Jayaraman and M. Jayachandran |
High Speed Circuit Design for 4-bit and 8-bit Unsigned Integer
Squarer.
Y.V.Ramana
Rao, N.Venkateswaran and S. Sundar |
Processor Selection for Embedded System Design.
S Ramanarayana
Reddy and Parimala N. |
|
Design and
Implementation of ECG Codec in FPGA.
T.Kalaivani M.S
and S.Arumugam |
A Low Power
Asynchronous Pipeline FIFO.
H.Mangalam,
K.Gunavathi and S.Subramanian |
Energy
Recovery Low Power CAM Design.
Josemin Bala.,
Poonkuzhali.N and Raja Paul Perinbam.J |
|
FPGA Based Multilayer Feedforward Neural Network and its
Applications for Odor Sensing
Mrinal
Sharadchandra Puranik |
Design and
FPGA implementation of wavepipelined distributed arithmetic based
filters.
G. Seetharaman,
B. Venkataramani and G. Lakshminarayanan
|
Performance Analysis of Encryption Algorithm in Software and
Hardware.
Sridhar
Krishnamurthy |
Implementation
of a cell scheduler for input buffered high speed unicast
switching.
Shanthi
Murugesh G
|
Design and
Implementation of High Speed Comparator.
Bolabattin
Narendra S |
VLSI Implementation of I2C Interface (Slave part).
Namita Mujumdar
and Akshata Mahale
|
|
VLSI Implementation of Canceling Maternal ECG from Fetal ECG.
N.J.R.Muniraj,
R.S.D.Wahida Banu and M.Ramya Sri |
|
Design Of MetaCore Reconfigurable Processor Using VHDL For DSP
Applications.
Karthigai
Lakshmi Shanmugavel
|