10^th VLSI Design And Test Symposium
VDAT2006

Analog Design

A Fully On-chip automatic gain control for RF-Transceivers complying IEEE 802.15.4, LR-WPAN
Harsh T, SIT Lonavala, Abhay N.A, BVP Pune and Tawade R, SCOE

A Novel Algorithm for Fault Diagnosis in Analog Circuits using Small Change Sensitivity Computation
Vishal Gupta, ST Microelectronics, Subash Chandra Bose, CEERI and Dinesh Jain, Analog Devices

An Improved Direct Injection Readout Structure for IR FPA
G.Rajahari, Anil K.Saini, S.C.Bose and Chandra Shekhar, CEERI

Highly Linear, Highly Efficient Power Amplifier Design Using Diode Nonlinear Capacitance
Mrunal. A.K., IITB , Makarand Shirasgaonkar, Qualcore Logic Ltd, Hyderabad and Rajendra Patrikar, VNIT, Nagpur

Design and Optimization of On-chip Spiral Inductor for Silicon Based RF IC'S
Genemala Haobijam and Roy Paily, IIT Guwahati

General Purpose Capacitive Sensing Circuit using Correlated Double sampling
Sandeep K, Chaitanya K and Navakanta Bhat, IISc, Bangalore

A Novel LO circuit for Sub-Harmonic Mixer
R.N.Biswas, Prof. C.Parikh, DA-IICT and G.P.Krishna Kishore, ATLAB Inc, Korea

Custom Design

Blind but not Color blind (CLDW06)
Madhuri Chowdhary

Wake-up Fresh Alarm – Part I (CLDW06)
Shwetha Shanbhag

Audible Colours (CLDW06)
Vasudha Chaurey and Chintan Agarwal, DA-IICT  (CLDW06)

Wake-up Fresh Alarm – Part II
Amandeep Singh, Punjab Engineering College (CLDW06)

EDA

Energy Efficient Application Specific Banked Register Files
Rakesh Nalluri and Preeti Ranjan Panda, IIT Delhi

Critical Path modeling for Dynamic Voltage Scaling (DVS) in Low Power Applications
Bishnu Prasad Das, Bharadwaj Amrutur and H.S. Jamadagni, CEDT, IISc Bangalore

Exact Method for Estimating Expected Settling Power in Sequential Circuits
Diganchal Chakraborty, P.P.Chakrabarti and Pallab Dasgupta, IIT Kharagpur

Waveform Analysis and Delay Prediction for CMOS driven RLC-Modeled VLSI Interconnect
B.K.Kaushik, IIT Roorkee, S.Sarkar, Modi Inst. of Tech. & Sc., Sikar and R.P.Agarwal

FPGA Architectures

Fault Tolerant FPGA using Redundant Columns
Neeraj Goel and Kolin Paul, IIT Delhi

FPGA Implementation of a new hardware architecture for Smoothing Two Dimensional Images
Narasimhan Venkateswaran, SVCE, Sriperumbudur and Y.V Ramana Rao, College of Engg, Anna University

Comparison of Compression techniques for FPGA configuration bit stream
Komala Soares, PCCE, Verna, Goa

Image Processing

A Dedicated Processor to Realize Inverse Radon Transform for CT Imaging
Abhishek Mitra and Swapna Banerjee, IIT Kharagpur

SOC implementation of the neural network based isolated word recognition
V. Amudha, B.Venkataramani, J.Karthick and C.Praveen, N.I.T, Tiruchirapalli

A Power-Efficient Architecture for the 2-D Discrete Wavelet Transform
Rahul Jain, CoWare India  and Preeti Ranjan Panda, IIT Delhi

Architectural Design and Implementation of a PC based Ultrasound Imaging System
Bodhisatwa Mazumdar , Aman Mediratta, Joydeep Bhattacharyya and Swapna Banerjee, IIT Kharagpur

Implementation of MPEG4 Video Decoder on a SoC Multimedia Processor
Prashanth P, Raghuveer P S, Celstream Technologies, Bangalore, Vinayak A.S. and C.R.Venugopal, SJCE, Mysore

Novel Architecture of Context Modeling for JPEG2000 and a comparison with Taubman's Architecture
Pratyush Aditya Kothamasu, Anand Gautam, A. Geeta Madhuri and Priya Khandelwal, DA-IICT, Gandhinagar

Design and Implementation of Morphological Operations and Median Filter for Image Processing Applications
Kapadia Payal Rohit, Nirma University, Ahmedabad, Raj Singh and Ravi Saini, CEERI

Design of Hardware Coprocessor for OTDR Application
Ponnmozhi Sampangi and Nitin Chandrachoodan, IIT Madras

Design and Study of an Electrostatic Torsion Micro Actuator for Beam Steering in Horizontal Plane
D. Vijaya Bhargava and Roy P. Paily, IIT Guwahati

A Novel Low Power Bus Encoding Technique for Minimizing RGB Transitions for LCD Display of Digital Camera
J.V.R. Ravindra, K.S. Sainarayanan and M.B. Srinivas, IIIT, Hyderabad

An efficient FPGA Implementation of a Cryptographic Hash Algorithm Based on Cellular Automata
Roshni Chatterjee and Dipanwita RoyChowdhury, IIT Kharagpur

Logic Design

A Novel Distributed and Interleaved FIFO for Source-synchronous Interconnect
Santosh Sood, Texas Instruments India, Mark Greenstreet and Resve Saleh, University of British Columbia, Canada

RF Energy Scavenging for Wireless Sensor Nodes
Shantanu Bhalerao, Abhishek Chaudhary, Raghavendra Deshmukh and Rajendra Patrikar, VNIT Nagpur

High Performance and Area Efficient n-BIT Tree Based Binary Squarer
Gopal Paul and Samir Satpathy, IIT Kharagpur

A Novel all Digital Phase Locked Loop for Phase Tracking in GPS Receivers
S Moorthi, K Pavithra, MIT Campus, Anna University and J Raja Paul Perinbam, CEG, Anna University

Low-power

An Energy-Efficient Packet Filtering Architecture for Wireless Sensor Nodes
Prashant Sonone and Saswat Chakrabarti, IIT Kharagpur

Design and Power-Performance Optimization of A Low Leakage Serial CAM
N. N. Mojumder, A. Dandapat and D. Mukhopadhyay, Jadavpur University

Design of an Efficient Low Power AES Engine for Zigbee Systems
Ninad B Kothari, T.S.B. Sudarshan, Shipra Bhal, Tejesh.E.C and S. Gururnarayanan, BITS Pilani

Physical Design

Efficient DRC for Verification of Large VLSI Layouts
Prosenjit Gupta and P.K. Ganesh, IIIT, Hyderabad

Cross talk Aware Multi-objective Optimal Routing for Island Style FPGA
Vineet Sahula, MNIT Jaipur and Rajesh Tiwari, Texas Instruments India

Fun with Faces (CLDW06)
Sridhar Moorkhandi

Smart Seeder (CLDW06)
Sumit J.Bhat

Sudoku (CLDW06)
Prashanth Kulkarni

Handling Trapezoidal Conductor Cross-sections in a Statistical Capacitance Extractor
Subramanian Rajagopalan and Shabbir Batterywala, Synopsys India

A Novel CMOS Compatible Three Terminal 3D Tunable Micro Inductor
V. Siva Rama Krishna, K.Jayant and Navakanta Bhat, IISc Bangalore

Integrated Stability Analysis Methods for Hybrid Systems
S. Jairam, Texas Instruments India and Navakanta Bhat, IISc Bangalore

Robust Design Techniques

Robust Power Delivery for Sub-100nm Integrated Circuits Embedded Tutorial
Thenappan Meyyappan, V Visvanathan, Texas Instruments India and S.K.Nandy, IISc Bangalore

Design and Analysis of Robust Clock Trees Embedded Tutorial
B.G.Madhusudan Rao, Jagdish Rao, Vish Viswanathan and Udayakumar H, Texas Instruments India

Technology

Study and Charecterization of Gallium Arsenide (GaAs) and Indium Phosphide (InP) Devices for Nanoapplications
E.N.Ganesh, P.K.Singh, BSA Crescent Engg college, Chennai and Lal Kishore, JNTU Hyderabad

Gas Sensor Interface ASIC on 0.7µm CMOS Technology
Shobi Bagga, Navakanta Bhat and S.Mohan, IISc Bangalore

Simulation Of Silicon Nanowire Field Effect Transistors, Carbon Nano Tube Field Effect Transistors and Comparison with Double Gate di-Electric silicon MOSFET
E.N.Ganesh, P.K.Singh, BSA Crescent Engg college, Chennai and Lal Kishore, JNTU Hyderabad

Test

Automatic Test Generation for Temporal Coverage Points Using a Stochastic Tree Model
Anindyasundar Nandi, Bhaskar Pal, Pallab Dasgupta and Partha P. Chakrabarti, IIT Kharagpur

Detecting Faults at the Time They Occur
Abhijeet Kumar, Sayantan Das, Pallab Dasgupta and P. P. Chakrabarti, IIT Khargpur

A Novel Unified Framework for Functional Verification of Processors Using Constraint Solvers
Debi Prasad, Archna Rai, Karthik. V, Senthil Kumar, V. Kamakoti, IIT Madras, Kailasnath S and Vivekanada Vedula, Intel Corporation, Austin

Constructing Online Testable Circuits Using Reversible Logic
Noor Mahammad, Siva Kumar Sastry, Shyam Shroff and V. Kamakoti, IIT Madras

Detection of Bridging Fault in Reversible Circuits
Hafizur Rahaman, Dipak K. Kole, Bengal Engg. & Science University, Debesh K. Das, Jadavpur University and Bhargab B. Bhattacharya, ISI Kolkata

On the Quality of Transition Fault Tests
Jais Abraham, InnoDes Solutions, Bangalore and Sandeep Jain, Texas Instruments India

Spectral Characterization of Functional Vectors for Gate-Level Fault Coverage Tests Embedded Tutorial
Nitin Yogi and Vishwani Agrawal, Auburn University