7th VLSI Design And Test Workshops
VDAT2003
August 28-30, 2003JN Tata Auditorium, IISc, Bangalore
Please visit VSI publications for details on VDAT proceedings.
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High Level and Logic Design
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01. |
The Growing Semiconductor Zoo: ASICS, Structured Arrays, FPGA, Processor Arrays, Platforms and Other Animalia |
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Raul Camposano |
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02. |
Concurrent Engineering Challenges and Opportunities IN System-on-a-chip Designs |
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Mahesh Mehendale |
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03. |
VLSI Education in India: Towards Excellence, Numbers, and Relevance |
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Chandra Shekhar |
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04. |
Semiconductor Design Outsourcing: Global trends and Indian Perspective |
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Vasudevan
Aghoramoorthy |
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05. |
A High Speed Efficient Signed/Unsigned N x N Bit Multiplier Based on Ancient Indian Vedic Mathematics |
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Himanshu Thapliyal and Vishal Verma |
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06. |
A Low Power Circuit to Generate Neuron Activation Function and its Derivative using Back Gate Effect |
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Amit K Gupta and Navakanta Bhat |
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07. |
Implementation Of A Deterministic Traffic Regulator |
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B.Bala Tripura Sundari and K.Murali Krishna |
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08. |
Implementation Of Blind Adaptive Filtering |
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N.J.R. Muniraj, R.S.D.Wahida Banu, N.Prabhakaran and P.Antony Vimal Dass |
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09. |
VLSI Design Simulation for Routing in Communication Network using Parallel Architecture |
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K.Paramasivam and K.Gunavathi |
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10. |
Comparative Analysis Of FPGA Performance |
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Dinesh Jain, S.C.Bose, and S.N.Sharan |
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11. |
Full Custom VLSI Implementation Of Golay and Extended Golay Encoder and Decoder |
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Annajirao Garimella |
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12. |
Application of Non-Equilibrium Green’s Function Formalism for Nanometric MOS Device Modeling and Simulation |
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B. Sharma and S. Dasgupta |
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13. |
Efficient Hardware Implementation of DCT Algorithms for Image Processing |
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Sigu Joseph |
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14. |
CMOS Camera with Electronic Shutter |
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Dhruba Chakrobarty, Srividya M B, Ambreesh Bhattad and Shivaling S Mahant-Shetti |
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15. |
A Fast 16-bit TSPC Adder in SOI CMOS |
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Lakshmikantha Holla V, Prasant Vallur, Poras T Balsara, Aravind K. Navada and Shashank Shastry |
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16. |
Carry circuitry for LUT-based FPGA (optimized for implementing finite field multipliers) |
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Varun Jindal and Alpana Agarwal |
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17. |
VLSI Implementation of Image Resizing Algorithms: Issues and Proposed Solutions |
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Indu. S. and Avinash K. R. |
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18. |
Design Flow and Methodology For 50M Gate ASIC |
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Alok Mehrotra, Lukas van Ginneken and Yatin Trivedi |
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19. |
Seamless Physical Design Flow Challenges and Solutions |
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Abhishek Pandey, Pradeep Cavale and A. Krupakaran |
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20. |
Partitioning of Circuits for Mapping onto Dynamically Reconfigurable FPGAs |
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K. Suresh and Santanu Chattopadhyay |
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21. |
A Unique Method For Dynamic Voltage Drop Analysis and Decoupling Capacitance Estimation |
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Rishi Bhooshan, Vikash Rakhecha, Binu Abraham, Vipul Singhal and Venugopal Puvvada |
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22. |
Useful Skew Management Inside Standard Cell Library |
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Amol Bidve and Pankaj Rohilla |
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23. |
Low Power Area-efficient Digital Counters |
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Chandra Mohan Umapathy |
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24. |
Design Challenges: Virtual Concatenation, Next Generation SONET/SDH |
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Nikhil Bhatia |
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25. |
The Energy Impact of Memory Port Allocation Decisions |
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Preeti Ranjan Panda |
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26. |
Power Management in Embedded Systems by an Efficient Online Idle Time Prediction Scheme |
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Rajeswari .P, Lakshmi Prabha. V, Elwin Chandra Monie |
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27. |
Novel Source-Independent Characterization Methodology for Embedded Software Energy Estimation |
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Syed Saif Abrar |
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28. |
Memory Architectures for Multiprocessor Embedded Systems |
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T.S. Rajesh Kumar, C.P. Ravikumar and R. Govindarajan |
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29. |
An Availability Model for Cosynthesis of Real Time Systems |
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S. Chakraverty |
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30. |
Reconfiguration in SOC With Programmbale Interocnnect |
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Meghana Desai |
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31. |
Static Approach for Peak Power Supply Noise Estimation |
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Ananth G Somayaji, Gaurav Thareja, Gautam Kapila and Vikash Rakhecha |
Physical Design and Technology
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01. |
Micro Electro Mechanical Systems (MEMS) : An Overview |
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Navakanta Bhat, C. Venkatesh and S. Pati |
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02. |
ESD in Sub-Micron Devices : Issues and Challenges |
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M.K. Radhakrishnan |
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03. |
Output Structure For Visible Imager Charge Coupled Devices |
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J. N. Roy |
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04. |
Modeling and Simulation of Quantum DOT Cellular Automata (QCA) for Future Nanometric Devices |
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Vishal K. Gupta and S. Dasgupta |
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05. |
Fabrication of Silicon Membrane at the Free End of Cantilever by Wet Anisotropic Etching |
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D. K. Maurya, K.Biswas, S.Das and S.Kal |
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06. |
A Laser Pre-amplified Optoelectronic Integrated Circuit (OEIC) Receiver Based on A Single MESFET Front-end |
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P. Chakrabarti, S. Nayak, D. Mishra and N. Jain |
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07. |
Channelsort: A Sorting Algorithm by Constructing Instances of Channel Routing Problem |
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Rajat K. Pal |
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08. |
A Graphical User Interface for Embedded Systems Design |
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S. Ramanarayana Reddy |
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09. |
Performance Analysis of FPGA |
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Dinesh Jain, S.C.Bose and S.N.Sharan |
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10. |
Power Optimal Clock Distribution in VLSI Circuits |
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H.Mangalam and K.Gunavathi |
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11. |
Design and Implementation of Passive RF Tag IC |
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Sutirtha Deb and Navakanta Bhat |
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12. |
Architectures for Noise Rejection in Level Shifting LVCMOS Input Buffers |
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Vikas Narang and Karthik Rajagopal |
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13. |
Techniques for Imp roving the Neural Optimization Method |
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Atanendu Sekhar Mandal and Basabi Bhaumik |
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14. |
Design for Manufacturability in Analog and Digital Library Development for High Semiconductor Reliability |
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Bedanta Choudhury |
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15. |
Impact of Gate to Source/Drain Overlap for Analog CMOS Circuit Application in sub-100nm Technology |
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C.S.Thakur and N. Bhat |
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16. |
Crosstalk Noise Closure in DSM Designs |
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Sreeram Chandrasekar, Ajoy Mandal, Sachin Shrivastava and Sornavalli Ramanathan |
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17. |
Design of High Data Rate Sigma-Delta Analog-to-Digital Converters |
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Abha Gupta, Lokesh Kumath and Dinesh Sharma |
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18. |
Automation of Analog Layout Generation and Design: Parameterized Cell Library Approach |
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Atul Pandey and Basabi Bhaumik |
Test and Verification
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01. |
Framework for Verifying Assertions Using Sequential ATPG |
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Ravi Kumar. Dasari and Krishna Kumar. D |
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02. |
Coverage Driven Functional Verification: To Speed Verification and Ensure Completeness |
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Pravin K. Dakhole |
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03. |
Test Data Compression for System-on-chip Using an Adaptive Compession Code |
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Nishant Soni and Santanu Chattopadhyay |
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04. |
Universal Test Set for Detection of Stuck-at Faults in GRM (Generalized Reed-Muller) Circuits |
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Hafizur Rahaman, Debesh K. Das and Bhargab B. Bhattacharya |
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05. |
Dual Processor Model Based Verification of SOC |
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Kamal Katiyar |
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06. |
It is Sufficient to Test 25-Percent of Faults |
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Vishwani D. Agrawal, A. V. S. S. Prasad and Madhusudan V. Atre |
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07. |
Test Cost Computation and Reduction Techniques |
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Jais Abraham |
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08. |
Redcued Pin Count Testing Using IEEE 1149.1 Environment |
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Asha B.P |
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09. |
Genetic Algorithmic Technique for Integrated Testing of Cores and Interconnects in SOC |
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Santanu Chattopadhyay and Shashi Shekhar Singh |
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A study of Parallel test application for core-based SoC designs |
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Anand Gangwar, Dasari Ravi Kumar and Shiva Kumar |
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11. |
Embedded Test For SOC Design |
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Shiva Kumar |
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12. |
Estimating the Fault Coverage of SOCs Using Module Coverage Data |
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Ajit Oke, Srinivas Kumar Vooka and Rubin A. Parekhji |
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13. |
Estimation of Test Power in Embedded Memories |
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Aman Kokrady, Rajat Mehrotra, C.P. Ravikumar and S. Phani Kumar |
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14. |
Detection & Analysis of Faults of CMOS Op- Amp |
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Dinesh Jain, S. C. Bose and Chandra Shekhar |
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