6^th VLSI Design And Test Workshops
VDAT2002

Logic and High-level Design

1. Tackling Signal Integrity Issues during DSM Design
B. Anantha Bhat

2. Introduction to Static Timing Analysis
Anidya Saha

3. An Extended Memory Architecture for Real-time Morphological Signal Processing
A. Durga Kishore and S. Srinivasan

4. Test And Interoperability of an Optical Signal Processor Using the Concept of Transforms
Dipnarayan Guha

5. Memory Exploration for Embedded Systems
T.S. Rajesh Kumar, R. Govindarajan, Manohar Sambandham and C.P. Ravikumar

6. CNB02: Bluetooth™ SoC
Praveen Saxena and Ranjit Yashwante

7. Integrated Design of an Image Processor Using DSP and ASIC Cores
G. Ramakrishna Reddy, Kumud Prakash Gupta and S. Srinivasan

8. A Simple Delay-Testable Design of Digital Summation Threshold Logic (DSTL) Array
Hafizur Rahaman, Debesh K. Das, and Bhargab B. Bhattacharya

9. Wireless LAN MAC (802.11 MAC) from CIPL
Prasad Joshi

10. Design of a Generic CELP Architecture
S. Madhusudhan, S. Monga, S.T.G. Ramakrishna, H.S. Jamadagni and Ashok Rao

11. ICie : Image Compression through Integrated Effort
S. Kambalimath

12. Design of an Embedded Microprocessor and its FPGA Implementation
Subhendra Basu

13. Design, Simulation and Synthesis of Fuzzy Controller Using VHDL
M.C. Bhuvaneswari, C. Karthik, V. Mahilchi Milir and R. Preethi

14. Carapace: Virus Resistant Computer Architecture
C. Chandramouli, P.B. Sudarshan, Murari Mani

15. Embedded RISC Processor Aimed at Wireless Applications
A.S. Anuroop, H.T. Madhusudhan, H. Manoj and P.R. Prasanna

16. Wallace Tree Squarer for DSP Applications
M.V.V. Satyanarayana, Annajirao Garimella and U.C. Niranjan

17. Computer Aided Fuzzy System Design and Simulation
Suthikshn Kumar

18. Hardware Designs for Video Compression Algorithms
S. Srinivasan

19. Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using a Reduced Constraint Set
T. Raja, M. Bushnell and Vishwani Agrawal

20. A Comparative Analysis of Flip-flop Architectures for Low-power Using Powersim
Jwalant Joshipura, Pankaj Rohilla, Bipin-Bandhu Malhan and Shubhyant Chaturvedi

21. Hardware Realization of a Digitally Controllable Neuron Activation Function and its Derivative for Extremely Low Power Application
Amit K. Gupta and Navakanta Bhat

22. Power Aware Characterization of Sequence of Input Vectors for Standard Cell Based Digital Circuits
P. K. Jain, D. Boolchandani and V. Sahula

23. Design of Broadband Controller for Residential Gateway Applications
Anindya Saha, Pankaj Saxena, Vikas Mishra, Rajesh Mundhada, Kamal Katiyar, Suresh Kumar and Arindam Saha

24. Effective Utilization of Memory in Shared Memory Architecture
Pramod A. Chordia

25. FIR Filter for A law and m law Data
Uma Mudengudi, Nalini Iyer and Meena M.

26. Finite Impulse Response Filter Design Using Chinese Remainder Theorem
Savitha

TOP

Physical Design

1. CMOS Technology Issues for Mixed Signal Applications
Navakanta Bhat

2. Design Synthesis and Physical Design of CMOS Operational Amplifier From User Specification
S.C. Bose, Abhijit Karmakar, Chandra Shekhar,V. Sunitha, Vigyan Jain, Gourav Jain, Vishal Kulshreshta and Robince Mathew

3. A Novel Approach To Unified RF Front End IC Design For Wireless Application
Prashant Admane, Biju Viswanathan, Manoj Patasani, and Nitin Garg

4. Comparative Study of RF Tuned Amplifier Performance with Different Inductor Configurations
R. Srinivasan, C. Venkatesh and Navakanta Bhat

5. A Novel Single HBT Front-End Based Monolithic Optical Receiver
P. Chakrabarti and R.K. Lal

6. Poly-reoxidation Process Step for Suppressing Edge Direct Tunneling (EDT) Through Ultrathin Gate Oxides in NMOSFETs
Kingsuk Maitra and Navakanta Bhat

7. Self-Consistent Solution of 2D-Poisson and Schrodinger Wave Equations for Nanometric MOSFET Modeling for VLSI/ULSI Purposes
S. Dasgupta and Deepesh Jain

8. Statistical Modeling of 0.1mm NMOS Device Characteristics for Implant Dose Variations
H.C. Srinivasaiah and Navakanta Bhat

9. Layout Design of Cascode Current Mirror With Improved Current Mismatch
D. Dhawan, D. Boolchandani and V. Sahula

10. A Search Scheme To Solve the Complex-Triangle Elimination (CTE) Problem For Unweighted Adjacency Graphs
S. Roy, S. Bandyopadhyay and U. Maulik

11. LaySeq: A New Representation for Non-Slicing Floorplans
S. Sathiamoorthy

12. eSpec: Specification Solution Driving Cell Create Flow
Narasimha Murthy, Poorvaja Ramani and P.S.Vijay Kumar

13. An Analytical Approach to Determine Cross-talk Noise in VLSI Chips
Mukund Madhav Agarwal and Manish Kumar Mathur

14. An Accelerator For FPGA Placement
Pritha Banerjee and Susmita Sur-Kolay

15. High Performance Routing for VLS Circuit Synthesis
Arpan Singha, Shekhar Ghosh, Achira Pal and Rajat K. Pal

16. Speed and Area Optimisation in SRAM Based FPGAS
G.K. Gopal, G. Panchakshari, Pavan Vithal Torvi and M.S. Bhat

17. Single Event Upset Response of a 0.09mm SRAM cell using 2D and 3D simulation
Prashant Kumar Saxena and Navakanta Bhat

18. Repeater Design Considerations for VLSI Interconnections
Rajeevan Chandel

19. Clock Tree - Wish List v/s Facts
Kamran Nabi Khan

20. On Evaluation of Parametric Yield for an Operational Transconductance Amplifier (OTA)
H.K. Sharma, L. Bhargava and V. Sahula

21. Two-dimensional Numerical Modeling of Sub-0.25 mm MOSFET for VLSI Applications
Yateen Kumar Suman and S. Dasgupta

22. Design of Dynamic MEMS Components
Rudra Pratap

23. MEMS for Space Applications: An Overview
S.V. Sharma, M.M. Nayak, Arun Batra and N.S. Dinesh

24. Trends in MEMS Fabrication Technology
K. Natarajan

25. Design, Modeling and Simulation of Porous Silicon MEMS Pressure Sensor for Space Applications
H. Saha, A.K. Pal, C. Pramanik and J. Das

TOP

Verification and Testing

1. Property Specification and Extraction within an Assertion-Based Verification Framework
C. Michael Chang and Harry D. Foster

2. System Level Verification of Present Day System on a Chip (SOC)
Vishal Dalal

3. Applying Model Checking for Verification of Small Controllers
Satish Panigatti, Ambar Gadkari and Rubin A. Parekhji

4. Using Formal Techniques for Identifying Uninitialized Registers in SOC Designs
Anindya Saha and Rajendra Ranmale

5. External Memory Interface: A Method for Functional Validation of Digital IP on Testchip
Sangeeta Sinha, Hitesh Shah, Rajesh Jeswani and Roopa Iyer

6. Design for Random Pattern Testability of Asynchronous Circuits
T. Jayakar, Charles Tobin, K. Satish and P. Sakthivel

7. An Introduction to P1500
J.R. Kotturashettar

8. Test Access Architecture Design for SOC
K. Sudarsana Reddy and Santanu Chattopadhyay

9. Unified BIST and Functional Optimisation in Behavioural Synthesis
Manoj Singh Gaur and Mark Zwolinski

10. Addressing the Power Concern in SOC Testing
C.P. Ravikumar

11. Boundary Scan Implementation at SOC Level
S. Madhusudan

12. Reuse of Single Stuck-at Fault Test Set For Transition Delay Fault Coverage
Prashant Ruparel

13. Effective Memory Test Solution for On-chip Cache Memories
B.P. Asha

14. Introduction to AC_EXTEST
Mrudula S. Torgalmath

15. A Comparison of Techniques for At-speed Testing
Prohor Chowdhury, Jais Abraham and Rubin A. Parekhji

16. Directed Search Based Optimal Test Vector Generation using Threshold Value Simulation
Prasad A.V.S.S., Madhusudan V. Atre

17. Formal Verification of Finite State Machines
Unni Chandran, D. Kuldeep and V. Sahula

18. Formal Verification for Validating Processor Architectures
Asheesh Shah

TOP

Education

1. Perspectives on VLSI Industry and Education in India
M.J. Zarabi

2. An Interdisciplinary Computer Engineering Curriculum
Vishwani D. Agrawal

3. Integration Issues in Implementation of Student LSI Design Projects
Shivaling S. Mahant-Shetti

4. Software Engineering Practices in Student Projects
Suresh Kumar

5. Project Management in VLSI Organizations
S. Ramesh

6. The New Recruits in an IT Company: A Behavioral Perspective
Anand Kasturi

7. VLSI Technology and Design: Frequently Not Asked Questions
Nagaraj Subramanyam

8. Continuing Evolution of High Tech Economy: How Can India Arrive at the Scene
Nitin Deo

9. Design Methodology for Multi-million Gate Hierarchical Designs
Suresh Honnenahalli