One-day Course on Circuit Marginalities

Dealing with VLSI Design and Circuit Marginalities during Test
UPDATED 25 June 2006

August 1, 2006, Kolkata, India

Venue: The SENATOR Hotel
15 Camac Street, Kolkata-700 017
Ph: +91-33-2289 3000/6, Fax: +91-33-2281 3093
Website: www.thesenatorhotel.com

1. Particulate Defects: Random particulates embedded into manufactured part. The particulates can come from suspended particles, contamination, CMP slurry or similar sources.
2. Sub-wavelength lithography: Sub-wavelength lithography can create corner rounding, line end shortening, missing lines, shorts, missing vias etc. These problems may be exacerbated by defocus that may result from non-planarity of the surface. CMP process may not leave a surface completely planar due to density, platten position vs. platten and carrier speed issues.
3. Design centering problems: VT, Leff, ILD thickness show variance across die, wafer and lot. Some of it is related to lithography and some of it is related to process metrology used during manufacturing. Typical design process deals with them by guardbanding a design. It is generally possible to predict the areas where performance or functionality problems will show up and therefore develop targeted test content.
4. Design Validation Problems: This can subcategorized into two buckets:

a. Design Approximations: Design process involves successive levels of approximation starting with cell characterization, interconnect extraction, model order reduction, simple delay equations, static timing analysis etc.. If scrutinized under microscope, these simplifications can all add up to an event that may cause circuit failure (examples will be provided).

b. Time to Market: With an explosive number of checking tools (signal integrity, power supply integrity, reliability checks such as electromigration or NBTI vulnerability etc.) the number of design violations that are flagged is very large. Most of these violations are false negatives and are due to overly simplifying assumptions used in the checking tools themselves. Designsers often ignore the violations to be in market on time and may potentially be swallowing a poison capsule.

Traditionally, digital testing of integrated semiconductor circuits have focused on particulate defects. Lately, it has been observed that a greater number of chip failures are due to Design related and lithography related issues.
This is the focus of this tutorial.

1. Introduction

2. Process Approximations

2.1. Modeling difficulties

2.2. Variations in Leff, Vt, ILD thickness, metal height and their impact on design

2.3. Subwavelength lithography issues