1. Introduction

6. Logic BIST

2. CAD tools used

7. Memory Test

3. Logic Test - Typical Fault Models

8. Test Compression

4. Advanced Faults Models

9. Fault diagnosis

5. Design for Test

10. Industrial Case Studies

1. Introduction

1.      Defects in DSM circuits

2.      Fault models

3.      Test methods

4.      Relationship between defect coverage and DPM

5.      Quality of test versus yield

6.      Power dissipation and peak supply current during test

5. Design for Test

1.      Scan designs – a mux-D based scan cell

2.      How scan works?

3.      DRC rule checks – uncontrollable clocks, etc.

4.      Scan and its benefits

5.      Other scan architectures – LSSD, clocked scan

6.      Resolving bus contention

7.      At-speed test application

8.      Scan-enable signal, pipelined scan-enable signal

9.      Slow shift/fast capture

10.  Enhanced scan architectures

11.  Logic BIST – an overall introduction.

12.  Boundary scan – how it works?

13.  Benefits of boundary scan

14.  Power conscious test techniques, test architectures

2. CAD tools used

1.      Logic simulators

2.      Fault simulators

3.      Test pattern generators

4.      Scan insertion tools

5.      Logic BIST

6.      RAM BIST

7.      Test Data Compression

3. Logic Test - Typical Fault Models

1.      Relation between defects and fault models

2.      Measures – fault coverage, test coverage, test efficiency, etc.

3.      Stuck-at Fault Model

4.      Test pattern generation/fault simulation

5.      Static and dynamic compaction

6.      Delay fault models – transition, path-delay and inline resistance fault models

7.      Launch off shift versus launch off capture

8.      False and multi-cycle paths

9.      Industrial experience with at-speed tests

10.  Iddq test sets

11.  Effectiveness of Iddq tests on nanometer designs

6. Logic BIST

1.      Requirements for implementing BIST

2.      Pattern Generation - Linear Feedback Shift Register

3.      Characteristics of pseudo-random patterns

4.      Output Compaction – Multiple Input Signature Register

5.      Aliasing probability

6.      Creating a BIST ready design

7.      Handling of X-states

8.      Handling of buses with multiple drivers

9.      Feedback loops, latches

10.  Random Pattern Resistant Faults

11.  Test Points – improve controllability and observability

12.  Overall Logic BIST Architecture

13.  Boundary scan and BIST

14.  A typical BIST session

15.  Fault simulation and signature calculation

16.  ATPG supplement patterns

4. Advanced Faults Models

1.      Bridging Faults

2.      Targeting Bridging Faults – n-detect test sets

3.      Test Generation for Bridging Faults

4.      Transistor stuck-on and stuck-open faults

5.      Test generation

6.      Propagation delay fault model

7.      Test generation

8.      Industrial experience, silicon results

7. Memory Test

1.      Different fault models for memories

2.      Conventional memory test algorithms

3.      Advanced memory test algorithms

·          Address decoder open tests

·          Byte write-enable mask tests

·          Multi-port memory tests

4.      Memory test techniques

·          Direct Access

·          Memory BIST

·          Macro Test

5.      Typical Memory BIST Architecture

6.      Methods for output evaluation

7.      Typical address generators

8.      Memory BIST collar

9.      At-speed test application

10.  Shared controllers – different test configurations

11.  Memory BIST through JTAG interface

12.  Localized address/data generation

13.  Programmability – algorithm specification, selection

14.  Field Programmable memory BIST

15.  Macro Test – test small memories via scan vectors

16.  At-speed test application using Macro Test

9. Fault diagnosis

1.      Why is diagnosis needed? How does it differ compared to test?

2.      Diagnosis at different levels – chip, board, system

3.      Scan chain diagnosis

4.      Logic diagnosis - methods

·          Fault dictionaries

·          Effect-Cause or Simulation Based Methods

5.      Diagnostic resolution

6.      Effect of compression on diagnosis

7.      Memory diagnosis

8.      Memory repair

9.      Design for manufacturability – what it means?

10.  DFM life cycle

11.  Current methods for yield learning

12.  Defect based testing

13.  Fault models based on physical data

14.  Mapping from logical faults to physical defects

15.  Closing the yield learning loop

16.  Industrial studies

8. Test Compression

1.      Conventional scan test – how does it work?

2.      ATE costs for scan vector application

3.      Test costs – data volume and scan test application time

4.      Scalability of scan based solution with increasing design complexity

5.      Requirements for a good compression scheme

6.      Conventional scan and ATPG process

7.      Scope for data volume reduction during ATPG

8.      Non-embedded forms of compression

9.      State of the art decompression techniques

10.  Stimuli repetition, stimuli conversion, and stimuli replication

11.  Stimuli encoding

12.  Reseeding of LFSRs

13.  Continuous Flow Decompression

14.  Ring generators

15.  Encoding capacity

16.  Embedded Deterministic Test (EDT) Architecture

17.  Advantages of using EDT - example

18.  Test response compaction – requirements?

19.  Time and Space compaction

20.  State of the art compaction techniques

21.  Selective compactor

22.  Handling of X-states and aliasing

23.  Finite memory compactors - convolutional and block compactors

24.  Advanced compression techniques – how one can achieve very high compression?

25.  Modular EDT architecture

26.  Burn-in test requirements

10. Industrial Case Studies

1.      SOC Design/test use

2.      SOC test methodology and flow

3.      Test re-use

4.      IEEE 1500 and how it facilitates test reuse

5.      Others…