4th Workshop on Design Verification Methodologies - Bangalore

UPDATED :
About the Workshop ... Program Schedule ... Speakers and Abstract

Program Schedule

… April 25 – Friday …

08.00 – 09:00 AM	Registration
09:00 – 09.30 AM	Inauguration
09.30 – 10.30 AM	Session I Keynote Talk – Pallab Dasgupta, IIT Kharagpur Model-Driven Integration: Putting together the bits and pieces of verification
10.30 – 11.00 AM	Tea
11.00 – 12.00 PM	Session II Low power Verification Abhijit Ray, Cadence Design Systems
12.00 – 01.00 PM	Session III Holistic Verification: Myth or The Magic Bullet? Pradip Thaker, Analog Devices Inc.
01.00 – 02.00 PM	Lunch
02.00 – 03.00 PM	Session IV Need for methodology in Functional Verification Srinivasan Venkataramanan, Synopsys India
03.00 – 03.30 PM	Tea
03.30 – 04.30 PM	Session V Realizing Design for debug infrastructure in complex SoC Haridas Vilakathra, NXP Semiconductors
04.30 – 05:30 PM	Session VI Verification Re-Use in RTL and SystemC IP Aniruddha Baljekar, NXP Semiconductors
End of Day-1

… April 26 – Saturday …

09.00 – 09:30 AM	Registration
09.30 – 10.30 AM	Session I Keynote Talk – Kaushik De, Synopsys India Verification of Clock Domain Crossing in Today’s Complex SOCs
10.30 – 11.00 AM	Tea
11.00 – 12.00 PM	Session II Coverage driven Verification Gurudutt Bansal, Cadence Design Systems
12.00 – 01.00 PM	Session III Verification Methodologies for Analog Design Modules/Blocks Prabhat Agarwal, Sankalp Semiconductor
01.00 – 02.00 PM	Lunch
02.00 – 03.00 PM	Session IV Increasing dynamic assertion-based verification productivity with formal techniques for compositional coverage analysis Ansuman Banerjee, Interra Systems India
03.00 – 03.30 PM	Tea
03.30 – 04.30 PM	Session V Systematic Approach for Verification of Complex SoC Badri Seshadri, Sainath Karlapalem, and Vishal Choudhary, NXP Semiconductors
04.30 – 6.00 PM	Panel Discussion Verifying monster SoC - Whose job is it anyway? Moderator: Raj Mitra, Texas Instruments India Panelists: Ish Dham, Texas Instruments India; Pradip Thaker, Analog Devices Inc.; Gurudutt Bansal, Cadence Design Systems; Srinivasan Venkataramanan, Synopsys India; Giri Raju, Wipro Technologies; and Sundaresan Kumbakonam, Broadcom Issues to be addressed in the panel are the following: How and where should the verification job be partitioned? IP vs SoC teams Design vs Verification teams Hardware vs Software teams Inhouse vs Outsourcing options Since the job does not wholly belong to one specific team, how is the responsibility and accountability tracked? That is, who gets the credit if the chip succeeds, who gets the blame if a respin occurs? What are the best practices that are followed for this partitioning and tracking? What are the areas of ambiguity and conflict? Are there any methodologies / technologies which can help to objectively answer these questions through measurable metrics? How does Formal verification influence the answers to these questions? How does mixed-signal further complicate the problem?
End of Workshop

Registration: Download announcement with registration form. (PDF 232 kb)

About the Workshop ... Program Schedule ... Speakers and Abstract
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