Organized by

VLSI Society of India

4^th Workshop on

Design Verification Methodologies

April 25-26, 2008

The Capitol Hotel, Rajbhavan Road, Opp GPO, Bangalore 560001

Tel: 080-22281234, 2228, 1800; FAX: 080-2225 9922, 2225, 9933

Nanotechnologies have ushered in System-On-Chip designs with 50 million gates.  Functional and timing verification of such designs is a formidable task. Design Verification has been known to be biggest contributor to the design cycle time.  Statistics also indicate that design respins are often due to functional bugs detected late.   

Cutting down the time for verification is one of the major goals of design teams across the globe.  Many new methodologies have emerged towards solving this problem.  This two-day workshop is intended as a forum to discuss the new trends and methodologies for Design Verification.  It is also a forum to share current practices in Design Verification.

The workshop is suitable for practitioners of Design Verification and for students/faculty who are engaged in VLSI design projects.

Speakers

Prabhat Agarwal, Sankalp Semiconductor

Aniruddha Baljekar, NXP Semiconductors

Ansuman Banerjee, Interra Systems India

Gurudutt Bansal, Cadence Design Systems

Vishal Choudhary, NXP Semiconductors

Pallab Dasgupta, IIT Kharagpur

Kaushik De, Synopsys India

Sainath Karlapalem, NXP Semiconductors

Raj Mitra, Texas Instruments India

Abhijit Ray, Cadence Design Systems

Badri Seshadri, NXP Semiconductors

Pradip Thaker, Analog Devices Inc.

Srinivasan Venkataramanan, Synopsys India

Haridas Vilakathra, NXP Semiconductors

History:

The first workshop in this series was held on November 25, 2005 at Hotel Atria, Bangalore and was attended by about 60 professionals:

http://vlsi-india.org/vsi/activities/dvw05_blr/

The second workshop was held during March 24-25, 2006 at Wipro Technologies, Pune and was attended by about 60 professionals:

http://vlsi-india.org/vsi/activities/dvm06_pne/

The third workshop was held during April 5-6, 2007 at I Square IT (I2IT), Pune Campus, and was attended by about 75 participants:

http://vlsi-india.org/vsi/activities/2007/dvm-pune-apr07/index.shtml

Registration: Download announcement with registration form. (PDF 232 kb)

Category 

Before March 31, 2008

After March 31, 2008

Professionals (Non-Members)

Rs. 4,000/-

Rs. 4,500/-

Professionals (VSI/ IEEE members)

Rs. 3,000/-

Rs. 3,500/-

Students/ Faculty (Non-members)

Rs. 2,500/-

Rs. 3,000/-

Students/ Faculty (VSI/ IEEE members)

Rs. 2,000/-

Rs. 2,500/-

Please also register using the online registration form at http://vlsi-india.org/vsi/activities/reg.shtml apart from sending the filled hardcopy of registration form, and to notify spot-registration.