Fourth VTU-VSI-ISA Confluence Meeting

February 28, 2007

Main Auditorium, R.V. College of Engineering, Bangalore, India

Anuradha Srinivasan completed BE (Electrical and Electronics) from BMS College of Engineering, Bangalore. She has 18 years of experience in VLSI, and has been with Intel for 4.5 years as Engineering manager. Currently, she is a member of Technical Staff in MGI.  Prior to this, she was with National Semiconductors for 6.5 yrs and worked on technologies from 1 micron to 65nm and primarily in the backend area (Synthesis, STA, Physical Design).

Design for Manufacturability - Challenges to Design Methodology

Abstract:

The presentation will provide an introduction to DFM and also talk about the challenges and changes to methodologies that this is bringing about for nanometer technology nodes.

C.P. Ravikumar is a senior technologist at TI India. He is also the secretary of the VLSI Society of India since 2003. More details about him can be found at http://cpravikumar.tripod.com

Multiprocessor Architectures for Embedded System-on-Chip Applications

Madhav Chikodikar is a senior manager for software development at Synplicity, Bangalore. He has around 12 years
of experience in logic synthesis for ASIC/FPGAs, timing analysis and HDL front-end development. Prior to this,
he was the lead developer with Synplicity, USA for their ASIC synthesis tool.  Madhav also worked with SASKEN
(formerly Silicon Automation Systems) on various projects in synthesis and HDL front-end development.

Synthesis of Digital systems

Abstract:

This presentation will cover different steps involved in mapping digital designs described at RTL level in HDLs such as Verilog or VHDL to ASICs and FPGAs. The presentation will briefly touch upon topics such as logic inference, module generation, two level and multi-level optimizations, technology mapping, timing analysis and timing optimizations. The presentation will also talk about the differences in mapping to FPGAs and ASICs.

Nisha PK graduated with a B.Tech in Electronics and Communication from Government Engineering College, Thrissur in 1998. She joined Texas Instruments, India, in 1999 where she has worked on design of telecommunication related IP, embedded memories, delay lock loops and Double Data Rate memories and interfaces.

High-speed Chip-to-chip Interfaces

Abstract:

As electronic equipment system-speed are increasing it is getting increasingly tougher to develop chip-to-chip data-transfer schemes, which can work reliably at high-speeds, in-spite of higher levels of noise jitter and signal integrity issues. In this presentation, we discuss various methods for chip-to-chip data exchange. These include schemes where the data is captured using the clock provided by the transmitter chip (source synchronous system), or schemes using a clock provided by the receiving chip (a non-source-synchronous system), or schemes using a clock provided externally to both transmit and receive, or a system where clock is recovered from the transmitted data. We also present the common concepts applicable to most of these schemes like jitter, ISI, SSO and other sources of noise, eye diagrams, link-timing budgets etc.

Arun Pradeep has Bachelor of Engineering [B.E] in Electronics and Communication and Master of Technology [M.Tech.] in Industrial Electronics. He has over 7.5 years experience in the IT industry. His Domain Experiences include Signal processing and embedded systems; audio, video and Imaging solutions for Digital TV, DVD and Mobile phones; short range communication systems [NFC] and navigation systems [GPS and DGPS]; identification systems for smart cards which includes Biometrics; Infotainment solution for car.

Handheld Digital Video Broadcast and Mobile T V

Abstract: The talk will mainly focus on advent of new mobile technology "TV on Mobile".  Concepts of Digital video broadcast will be covered and extension of DVB to handhelds will be explained. Focus will be on architecture, design consideration and software stack. Finally cost models and billing models of consumer and service providers will be covered.

Razak Mohmmad Ali has worked for more than six years at Altera Semiconductor India, and is a University Program Manager looking after South-East Asia Pacific region. He obtained his MS from Texas, Austin; M.Sc. from IIT Khargpur, and MBA from Santa Clara University, USA.

Timing Analysis techniques in FPGAs

Abstract:

In this presentation we will investigate various techniques used in timing analysis of digital circuits implemented in FPGAs. Techniques for timing optimization and timing closure will be discussed. We will also briefly discuss how to incorporate Synopys Design Constraint (SDC) into FPGA design flow using the Timequest tool.