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Day-1 –
Thursday, December 13, 2007
Interconnect RC parameters are significant
components of circuit performance, signal integrity and reliability in IC
design. Due to manufacturability and reliability issues, the effective
dielectric constant of the inter-metal dielectric is not scaling
commensurate with the technology scaling predicted in the ITRS roadmap.
Metal resistance is also increasing due to electron scattering effects,
which exacerbates the interconnect RC scaling issues in sub-100nm technology
nodes. The increase in contact and via resistance further aggravates the
technology entitlement issues. Although reverse scaling is an attractive
option for high performance designs, area entitlement is an issue in routing
limited designs. Overall improvement in interconnect performance relies more
and more on architecture & design techniques and novel interconnect schemes.
The sessions on Day 1 review interconnect scaling, signal integrity,
physical design, architecture solutions and optical interconnect.
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08.00 - 08:30 AM |
Registration |
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08:30 - 09:00 AM |
Inauguration
Interconnect Design and
Variability in Nanometer Era
Nagaraj NS
and CP Ravikumar |
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09:00 - 10:00 AM |
Big Challenges for the
Semiconductor Industry: Bridging Design and Manufacturing
Juan C. Rey, Mentor Graphics Corporation, Srinivas Mandavilli, Mentor Graphics India
Chair: N.S.Nagaraj, Texas Instruments Inc., Dallas
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10:00 - 10:15 AM |
Break |
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10:15 - 11:15 AM |
On-Chip Global
Interconnect Using Transmission Line
Kazuya Masu,
Tokyo Institute of Technology
Chair: N.S.Nagaraj, Texas Instruments Inc., Dallas
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11:15 - 12:15 PM |
Interconnect Parasitic
RLC and delay Variability below 90nm, Physical Origins and its Impact on
the Future Geometry Scaling
Ersed Ackasu,
OEA International, Inc.
Chair: N.S.Nagaraj, Texas Instruments Inc., Dallas
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12:15 - 01:00 PM |
Lunch |
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01:00 - 02:00 PM |
Interconnect variability
- A front-end perspective
Noel Menezes,
Intel Corporation
Chair: Shabbir Batterywala, Synopsys India
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02:00 - 03:00 PM |
Thermal Challenges In
Integrated Circuit Design
Sachin Sapatnekar,
University of Minnesota
Chair: Shabbir Batterywala, Synopsys India
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03:00 - 03:15 PM |
Break |
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03:15 - 04:15 PM |
Quality Now Requires -
Small Delay Fault Model
Tom Williams, Synopsys Inc
Chair: C.P.Ravikumar, Texas Instruments India
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04:15 - 05:30 PM |
Panel Discussion:
Managing Variability - should it be a Design Issue or a Test Issue?
Participants:
Kazuya Masu,
Ersed Ackasu,
Noel Menezes,
Sachin Sapatnekar,
Tom Williams, Nagaraj N.S.
Chair:
C.P. Ravikumar, Texas Instruments India |
Day-2 – Friday,
December 14, 2007
Design For Manufacturability Yield (DFM&Y)
has received much attention in sub-100nm technologies. Addressing the
challenges in systematic and random process variations is a critical part of
the DFM&Y strategy. Global and local variations in transistors have been
analyzed in analog circuits for several years and recently extended to
large-scale digital circuits in the form of Statistical Static Timing
Analysis (SSTA). In additional to random variations, systematic variations
such as stress induced variations need to be considered. In addition to
transistor variations, interconnect variations due to Chemical Mechanical
Polishing (CMP), etch and process bias are important considerations.
Structured layout, variation-aware and variation tolerant design techniques
help mitigate variability issues. The sessions on Day 2 review key aspects
of lithography, CMP, etch and stress induced variations, SSTA methods and
variation tolerant design techniques.
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08.00 - 08:30 AM |
Registration |
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08:30 - 09:30 AM |
Process-aware Timing and
Power Analysis and Optimization
Steffen Rochel, Blaze DFM Inc.,
Chair: Vivek Raghavan, Magma Design Corporation
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09:30 - 10:30 AM |
Addressing
pattern-dependent variability in design using model-based DFM tools
Nishath Verghese
and Atul Sharan, Cadence Design Systems
Chair: Vivek Raghavan, Magma Design Corporation
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10:30 - 10:45 AM |
Break |
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10:45 - 11:45 AM |
Design-In-Reliability for Interconnect
Nagaraj N.S., Texas Instruments Inc., Dallas, Palkesh Jain and Gautam Kapila TI India
Chair: Venugopal Puvvada, Quallcomm India Inc.
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11:45 - 12:45 PM |
On the use of
standardized interconnect in VLSI Systems
Madhav P. Desai,
IIT Bombay and Vani Prasad, Freescale Semiconductor
Chair: Venugopal Puvvada, Quallcomm India Inc.
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12:45 - 02:00 PM |
Lunch |
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02:00 - 03:00 PM |
Clocking in GHz designs
Vidyasagar Ganesan,
AMD
Chair: Vish Visvanathan, Texas Instruments India
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03:00 - 04:00 PM |
Interconnect Design –
Packaging Perspectives and Considerations
Vish Sundararaman,
Texas Instruments Inc., Dallas
Chair: Vish Visvanathan, Texas Instruments India
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04:00 - 04:15 PM |
Break |
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04:15 - 05:30 PM |
Panel Discussion:
Participants:
Steffen Rochel, Vish
Sundararaman, Nishath Verghese,
Atul Sharan, Madhav P. Desai,
Vidyasagar Ganesan, Palkesh Jain, Gautam Kapila, Nagaraj
N.S. and C.P. Ravikumar
Chair:
Vish Visvanathan, Texas Instruments India |
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