Abstract

Big Challenges for the Semiconductor Industry: Bridging Design and Manufacturing

Juan C. Rey, Mentor Graphics Corporation

Srinivas Mandavilli, Mentor Graphics India

The semiconductor industry is changing at a fast pace when moving to 45 nm and beyond. The long announced DFM (Design for Manufacturability) challenges are reaching a level of consolidation not seen before, as the industry is moving from the independent development of tools and flows to standardization of definitions, and interfaces. This presentation will summarize the CAD tools developed at the interface of design and manufacturing, describe some of the directions being considered to help minimize variability in the physical design and post-tapeout flows, and introduce some of the changes under consideration for 32 nm and beyond.

On-Chip Global Interconnect Using Transmission Line

Kazuya Masu, Tokyo Institute of Technology

On chip global interconnect is usually designed based on RC lumped model and the global interconnect is divided by repeaters to improve the delay time.  Because of scaling of metal width/height and ILD spacing, the delay time of global interconnect becomes worse as ITRS has anticipated.  Introducing the transmission line concept into global interconnect is a possible candidate to improve the global delay and power consumption.  In this lecture, the possible structure of transmission line interconnect with reducing the cross talk, circuits of driver and receiver, circuit performance of transmission line interconnect, comparison of interconnect performance of the transmission line and optical interconnect are discussed.

Interconnect Parasitic RLC and delay Variability below 90nm, Physical Origins and its Impact on the Future Geometry Scaling

Ersed Ackasu, OEA International, Inc.

As the geometries shrink, the statistical variations due to processing starts to play a more significant role in the metal geometry predictability. In addition to that interconnect metal thickness and its width depends on the width printed on the mask as well as on the proximity metal density and its geometry. In the first part of this paper geometry variations due to both of these effects on the parasitic capacitance, resistance, self and mutual inductance and their combined effect on the interconnect delay variability is discussed using three-dimensional extraction techniques. Floating metal effects is also discussed with using appropriate boundary conditions in the Laplace equation for capacitance extraction. In addition to that electrical properties of the interconnect, such as resistivity also becomes width dependent which complicates the problem even more. Assuming that the atom-to-atom spacing is ~5-6 Angstroms, 65nm becomes roughly in the order of 100 atoms wide and this number is shrinking to the order of 50 atoms in finer lithographies! In this case one atom variation in the width will translate to 2% variation. The second part of the paper discusses the effects of the discontinuous nature of the matter on the electrical properties of the interconnect and investigates the bounds of its variability and its resulting discontinuous nature.

Interconnect variability - A front-end perspective

Noel Menezes, Intel Corporation

The lack of correlation in the variations of the metal layers comprising the segments of typical multi-terminal interconnect has led to multi-corner timing analysis being routinely applied.  This analysis is primarily carried out to prevent yield problems due to the parametric variations that arise from back-end (interconnect) manufacturing steps. The complexity of analysis at multiple process corners is dominated by the large number of potential corners -- exponential in the number of layers -- caused by interconnect variations. This talk will instead focus on the subtle yet strong interaction between transistor (front-end) and interconnect variations that has not received adequate attention in the design community. Simple, elegant design techniques that can alleviate interconnect variation problems will also be presented.

Thermal Challenges In Integrated Circuit Design

Sachin Sapatnekar, University of Minnesota

As integrated circuit technologies scale, thermal issues are an increasingly important source of uncertainty.  Thermally induced effects include short-term changes in the circuit delay and leakage power, as well as accelerated long-term aging that lead to reliability problems.  This talk will begin by describing techniques for on-chip thermal analysis in 2D as well as 3D structures.  Next, methods that measure the impact of thermal changes on long term and short term performance metrics will be overviewed.  Finally, design techniques for recovering from these problems will be presented.

Quality Now Requires - Small Delay Fault Model

Tom Williams, Synopsys Inc

The concept of small delay faults has been discussed for more than 20 years. Methods for determining the relative merits of delay test sets have also been known for 20 years. This was first proposed by Park, Mercer and Williams in 1988. Until recently this area of testing has been considered unnecessary. Today many groups want to use small delay fault testing to achieve high-quality levels. This work will review the derivation of the quality metrics and address how they are used today. Testing for small delay defects requires ATPG-FS¹ tools to understand the design’s timing information such that transition delay faults² can be detected along longer paths. Timing information is analyzed for use in test automation tools to test for small delay defects. Fundamentals of static timing analysis are analyzed with regard to test. This paper concludes that Signal Integrity³ information can be ignored by test automation tools when timing information is used to guide ATPG tools towards longer paths. This work also shows that a lack of understanding of clock trees in the long path ATPG algorithm leads to incorrect results.

¹ Automatic Test Pattern Generation (ATPG) is the process of creating a test and Fault Simulation (FS) is the process of determining which modeled failures are detected by tests.
² A transition fault represents a lumped-delay-defect (slow to rise or slow to fall) on a given net of the design.
³ Signal Integrity is used in this paper to mean the impact of capacitive coupling on timing.

Process-aware Timing and Power Analysis and Optimization

Steffen Rochel, Blaze DFM Inc.,

Addressing pattern-dependent variability in design using model-based DFM tools

Nishath Verghese and Atul Sharan, Cadence

As designs migrate to 65nm process technology and below, the impact of systematic manufacturing effects on design functionality and performance is increasing substantially.  Manufacturing design layout features of sub-wavelength feature sizes requires a continual increase in the use of optical proximity correction (OPC) and resolution enhancement techniques (RET). Manufacturers today use sophisticated simulation software and model-based methods to perform OPC and RET in mask making. However, designers of chip layout are still using rules (to mimic these models) provided to them by manufacturers - for chip routing, DRC, layout parameter extraction (LPE) and parasitic extraction (RCX). As geometries shrink, the impact of neighboring layout patterns on the printability and electrical characteristics of a drawn shape can no longer be captured effectively using rules. Models of printability and performance impact on transistors and wires due to layout patterns must be made available to designers. “Model-based DFM” tools provide such capabilities to chip designers. Using models calibrated to manufacturing processes, these tools allow designers to predict the systematic impact of pattern-dependent variability on the functionality and performance of their chips. They can be used in conjunction with existing routers, extractors and timing tools to provide insight into the impact of manufacturing effects like lithography, etch, stress and CMP. This talk will focus on methods and tools for model-based analysis and optimization of designs for pattern-dependent variability.

Design-In-Reliability for Interconnect

Nagaraj N.S., Texas Instruments Inc., Dallas, Palkesh Jain and Gautam Kapila TI India

The talk walks through the basic concepts of reliability, focusing on the interconnect. As a background, we revisit conventional interconnect reliability guidelines, specifically, electro migration, and related checking procedures. The challenges thrown in to these approaches are highlighted in the light of continued technology scaling and design scaling viewpoint. Power management and statistical process variations are taken as point examples to substantiate the challenges and possible solutions to them are outlined. We also bring in the system reliability perspective and highlight the importance of considering the final application and the complexity of the overall design in the reliability assessment.

Subsequently, we discuss the advances aspects of interplay between interconnect and transistor reliability. Specifically, how the parasitics from interconnects (R, L and C) affect the transistor reliability, namely, gate oxide reliability (TDDB) and negative bias temperature instability (NBTI). On the other hand, the interconnect reliability itself is a function of the transistor age, presenting a case of the joint optimization of the system reliability. The talk eventually motivates designers to move away from traditional sign-off reliability thought process, to a more involved, design-in approach, to achieve higher design and technology entitlement.

On the use of standardized interconnect in VLSI Systems

Madhav P. Desai, IIT Bombay and Vani Prasad, Freescale Semiconductor

As VLSI technology scales, wire behaviour tends to become a greater factor in determining the correctness and performance of complex VLSI systems.  In order to understand the impact of wire behaviour on the system, it is necessary to accurately model and simulate interconnect in such systems. The accurate modeling and simulation of the interconnect are computationally intensive tasks and often cannot be carried out at early stages in the design flow (such as floorplanning) due to incomplete information.  Thus, the system designer often faces the risk of expensive design iterations until she/he achieves design closure. In this talk, we examine the feasibility of using standardized interconnect in the construction of VLSI systems. The advantage of standardization is the availability of pre-characterized and accurate models, which will have an immediate impact on the design closure problem. The potential disadvantages are the possible loss of performance due to standardization and the usability of the standardized interconnect in practical design flows. In this talk we propose a standardized interconnect library consisting only of point-to-point connections.  We show that these standardized elements are near delay-optimal (to within two inverter delays of the best possible solution), and further, demonstrate that the bandwidth offered by these elements is superior to that offered by ad-hoc solutions.  We also show that complex routes can be constructed from these standard elements using a simple cut-and-splice routing model, which leads to near-optimal routing delays. Further, these conclusions are valid even as technology scales into the deep sub-100nm range.  We conclude that standardization of interconnect is feasible and offers a viable solution to the interconnect problem in VLSI system design.

Clocking in GHz designs

Vidyasagar Ganesan, AMD

Variation has always been a part of the semiconductor business. However at sub 100nm the process and environmental variation pose tremendous challenges to designer in meeting the Performance, power and yield targets. In multi GHZ designs, clock distribution needs to have low skew, factoring the variations from device, interconnect and transient conditions. In this talk we will explore clocking schemes, its impact to variations and techniques to minimize them.

Interconnect Design – Packaging Perspectives and Considerations

Vish Sundararaman, Texas Instruments Inc., Dallas

Electronic packaging represents a significant and integral portion of the IC interconnect bridging the silicon device and functionality to the OEM / end-user application.  Packaging technologies continue to evolve to keep pace with the ever-increasing complexity and trends in the semiconductor industry towards miniaturization, integration and densification.  In this workshop, a general overview of the key packaging capabilities, both existing and emerging, will be introduced.  Emphasis will be placed on typical interactions between key post-fab package and assembly processes, materials, design aspects and the overall and intended interconnect design and performance.  The content of this workshop will be generic in nature to preserve global impact and perspective while aiming to illustrate the increasingly blurred boundary between silicon and package, and hence highlight the need to include packaging aspects into interconnect design.