UPDATED: 3 April 2007
About the Workshop ... Program Schedule ... Speaker details
Third Design Verification Methodologies WorkshopApril 5-6, 2007I Square IT Pune Campus, Maharashtra |
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08.00 – 09:00 AM |
Registration |
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09:00 – 09.30 AM |
Inauguration |
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09.30 – 10.30 AM |
Session I Keynote Talk – Static Checker Technology: How it can help in Design Verification Dr.Kaushik De, Verification Business Unit, Synopsys India |
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10.30 – 11.00 AM |
Tea |
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11.00 – 12.00 PM |
Session II Formal Protocol verification using Assertion IPs Tarun Garg, Cadence Design Systems |
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12:00 – 12.30 PM |
Session III SystemVerilog and SystemC for an Effective Design and Verification Shanthamoorthi Velusamy, Wipro Technologies |
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12.30 – 01:00 PM |
Session IV System Level Analysis and Verification: An Industry Perspective Bhaskar Karmakar, Texas Instruments India |
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01.00 – 02.00 PM |
Lunch |
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02.00 – 03.00 PM |
Session V: Keynote Talk – Challenges in Formal Methods for Intent Specification and Verification Dr. P.P.Chakrabarti – IIT Kharagpur |
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03.00 – 03.30 PM |
Tea |
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03.30 – 04.30 PM |
Session VI Tutorial - An Expedition to The System Modeling World Desingh D Balasubramanian, Poseidon-Systems India |
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04.30 – 05.30 PM |
Session VII Verification of the 80 core, 1.28 Teraflop Network-on-Chip in 65nm CMOS Tiju Jacob, Intel Corporation |
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End of Day-1 |
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08.30 – 09:30 AM |
Registration |
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09.30 – 10.30 AM |
Session I: Keynote Talk – Battling State Space Explosion: The Road Traveled and The Road Ahead Dr. Supratik Chakraborty – IIT Bombay |
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10.30 – 11.00 AM |
Tea |
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11.00 – 11.45 AM |
Session II Reusable Debug Infrastructure in Multi-core SoC Haridas Vilakathra, SoC Design Technology, NXP Semiconductors India |
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11.45 – 12.15 PM |
Session III Sub-System Design and Verification Methodology Manikandan Panchapakesan, NXP Semicondutors India |
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12:15 – 01.00 PM |
Session IV Configurable IP! - Overcoming the Verification Challenges Vishwanath B and Ankush Jain, NXP Semicondutors India |
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01.00 – 02.00 PM |
Lunch |
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02.00 – 03.00 PM |
Session V SystemVerilog based Verification using VMM: An Overview Aditya Kher, Synopsys India |
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03.00 – 03.30 PM |
Tea |
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03.30 – 04.30 PM |
Session VI Challenge in Mixed-Signal/Analog Verifications , Roads Ahead Mrinal Das, Sankalp Semiconductor, India |
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04.30 – 5.30 PM |
Panel Discussion Details TBD
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End of Workshop |
Please also register using the online registration form at
http://vlsi-india.org/vsi/activities/reg.shtml
apart from sending the filled
hardcopy of registration form, and to notify spot-registration. Download Announcement with Registration form. PDF 160 KB
About the Workshop ... Program Schedule ... Speaker details
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