Third Design Verification Methodologies Workshop

April 5-6, 2007

I Square IT Pune Campus, Maharashtra

VLSI Society of India

http://vlsi-india.org/vsi/

Organized by VLSI Society of India and
International Institute of Information Technology, (I Square IT) Pune

I²IT Pune

www.isquareit.ac.in/

Supported by IEEE Pune Subsection

Corporate Sponsor

Wipro Technologies, Pune

Nanotechnologies have ushered in System-On-Chip designs with 50 million gates.  Functional and timing verification of such designs is a formidable task. Design Verification has been known to be biggest contributor to the design cycle time.  Statistics also indicate that design respins are often due to functional bugs detected late.   Cutting down the time for verification is one of the major goals of design teams across the globe.  Many new methodologies have emerged towards solving this problem.  This two-day workshop is intended as a forum to discuss the new trends and methodologies for Design Verification.  It is also a forum to share current practices in Design Verification.

The workshop is suitable for practitioners of Design Verification and for students/faculty who are engaged in VLSI design projects.

Venue

International Institute of Information Technology

Microelectronics and VLSI, I2IT, Pune

P-14, Rajiv Gandhi Infotech Park, Hinjewadi

Pune 411057, Maharashtra

Phone: 020-22933441 FAX: 020-22934191

How to reach I2IT Campus: Weblink     PDF 80 KB

Speakers

Dr. P.P.Chakrabarti  - IIT Kharagpur

Tarun Garg, Cadence Design Systems

Shanthamoorthi Velusamy, Wipro Technologies

Bhaskar Karmakar, Texas Instruments India

Dr.Kaushik De, Verification Business Unit, Synopsys India

Desingh D Balasubramanian, Poseidon-Systems India

Tiju Jacob, Intel Corporation

Dr. Supratik Chakraborty  - IIT Bombay

Haridas V., SoC Design Technology, NXP Semiconductors India

Manikandan Panchapakesan, NXP Semicondutors India

Vishwanath B and Ankush Jain, NXP Semicondutors India

Aditya Kher, Synopsys India

Mrinal Das, Sankalp Semiconductor

History:

The first workshop in this series was held on November 25, 2005 at Hotel Atria, Bangalore and was attended by about 60 professionals. The details of the previous workshop can be found at: DVM 2005

The second workshop was held during March 24-25, 2006 at Wipro Technologies, Pune and was attended by about 60 professionals. The details of the previous workshop can be found at: DVM 2006

For accommodation, please contact: Mr.Harish, I²IT Pune (harishm@isquareit.ac.in Phone: 09890834503 updated)

For registration, please contact: Mr. Praveen, I²IT Pune (praveench@isquareit.ac.in Phone: 09860676053)

Mr. Vamsi Krishna, I²IT Pune (npvamsi@isquareit.ac.in)

Before March 15, 2007

After March 15, 2007

Professionals (Non-Members)

Rs. 4,000/-

Rs. 4,500/-

Professionals (VSI/ IEEE members)

Rs. 3,000/-

Rs. 3,500/-

Students/ Faculty (Non-members)

Rs. 2,500/-

Rs. 3,000/-

Students/ Faculty (VSI/ IEEE members)

Rs. 2,000/-

Rs. 2,500/-

Please also register using the online registration form at http://vlsi-india.org/vsi/activities/reg.shtml apart from sending the filled hardcopy of registration form, and to notify spot-registration. Download Announcement with Registration form. PDF 160 KB