UPDATED : 23 May 2007
About the Seminar ... Topics

Note: No more new/ spot Registrations for the event are accepted.

Organized by http://vlsi-india.org/vsi VLSI Society of India

One-day Seminar on Design For Manufacturability and Reliability July 27, 2007, Kolkata, India Venue: The SENATOR Hotel

In cooperation with http://www.ieee.org

Design For Manufacturability and Reliability Duration: Full day   Registration 8.30 AM – 9.30 AM Tutorial 9.30 AM – 5.30 PM Morning Coffee break 11.00 AM -11.30 AM Lunch break 1.00 PM – 2.00 PM Afternoon Coffee Break 3.30 PM – 4.00 PM     Target Audience: Practicing Engineers, Design Professionals, Students and Academics   Topics:   1. Introduction   2. Manufacturing Defects v      Particulate defects v      Large parametric excursion v      Lithographic aberrations (e.g., problems related to diffraction, focal image plane and dose)   3. Defect Modeling v      For critical yield (critical area calculation and optical proximity correction) v      For parametric yield (litho and resist simulation)   4. Yield Models (with and w/o redundancy).   5. Defect Tolerance Techniques v      Architecture based techniques (memories, processors, PLAs etc) v      Circuit/layout hardening techniques v      Algorithm based tolerance v      Statistical methods   6. Reliability Issues v      Hot Carrier v      Thermal v      Electro-migration v      Gate oxide problems v      Testing for reliability problems v      Soft-error   Download announcement with registration form PDF 94KB Please also register using the online registration form at http://vlsi-india.org/vsi/activities/reg.shtml apart from sending the filled hardcopy of registration form. Spot-registration subject to availability at the after deadline rates against DD or Cash.