UPDATED : 23 May 2007
About the Seminar ... Topics

Note: No more new/ spot Registrations for the event are accepted.

Organized by http://vlsi-india.org/vsi VLSI Society of India	One-day Seminar on Design For Manufacturability and Reliability July 27, 2007, Kolkata, India Venue: The SENATOR Hotel	In cooperation with http://www.ieee.org
15 Camac Street, Kolkata-700 017 - Ph: +91-33-2289 3000/6, Fax: +91-33-2281 3093 - Website: www.thesenatorhotel.com
Summary: Reliability, Redundancy, Yield, Fault Tolerance are somewhat overlapping yet very distinct subjects. Traditionally, a product is considered reliable if it has no early-life failure (infant mortality), no wear out before expected end of life and a very low rate of failure during its useful life. Reliability is characteristic of a product after it is shipped and is a function of component quality as well as its design. Design for Reliability is an exercise in exploiting and managing redundancy. Redundancy is nominally defined as having more resource than is minimally necessary. Yield on the other hand is defined as the number of good parts obtained from a complex manufacturing process against the total number of parts that are produced. Yield is a function of manufacturing quality and the goodness of the test process. Like reliability, yield can also be improved through design process. This is commonly called Design for Manufacturability. Design for Manufacturability includes understanding and modeling the errors that result from manufacturing process, calibrating those models and avoiding error mechanisms through design process. Physical Design Rules can be construed as first order Design for Manufacturability practice. However, in current semiconductor manufacturing processes, it has become more involved than that. In current semiconductor manufacturing processes, the light source has a greater wavelength than feature size. Thus layout designs must incorporate features to exploit optical diffraction to improve yield. In this tutorial, we will explore these issues at depth.
Targeted Audience: Targeted audience is practicing engineers, students and academics. Some physical design knowledge is helpful but not necessary. The topics covered are listed below. Handout will include a list of references for further exploration of the topic.
Course conducted by:   Sandip Kundu, University of Massachusetts, USA   Sandip Kundu is a Professor of Electrical and Computer Engineering at University of Massachusetts, Amherst. Previously, he was a Principal Engineer at Intel and Research Staff Member at IBM Yorktown. He has published more than 70 papers in diverse areas including VLSI design, Testing, CAD and Coding & Information Theory. Sandip holds several US patents. He has given more than 10 tutorials at international conferences such as the VLSI Test Symposium, International Test Conference, DATE, and others. His major accomplishments include Intel ultra-drowsy technology (US Patent 6,715,091); mixed synchronous and asynchronous circuit simulation technology used at Intel (US patent 6,973,422), commercial CAD software called GateMakerÔ (sole author) that is marketed by Cadence after its acquisition from IBM and t-SyEC/AUED codes used in optical communications. He was the Technical Program Chair of ICCD in 2000 and General Chair in 2001. He served as a General Chair of the International Conference on VLSI Design, 2005. Prof. Kundu is currently an associate editor of IEEE Transactions on Computers.
Registration Fee Before June 20, 2007 After June 20, 2007 Professionals (Non- Members) Rs.3,000/- Professionals (Non- Members) Rs.3,500/- Professionals (VSI/ IEEE members) Rs.2,500/- Professionals (VSI/ IEEE members) Rs.3,000/- Students/Faculty  (Non-members) Rs.1,500/- Students/Faculty  (Non-members) Rs.2,000/- Students/Faculty  (Members of VSI/ IEEE) Rs.1,000/- Students/Faculty  (Members of VSI/ IEEE) Rs.1,500/-
The registration fee includes registration material, softcopy of notes, lunch and refreshments. Mode of Payment: Demand Draft, drawn in favor of  “VLSI Society of India” payable at Bangalore. Participants from Kolkata may send the DD to Dr.Partha Prathim Das, Interra Systems, Kolkata to the address mentioned in the form. Please also register using the online registration form at http://vlsi-india.org/vsi/activities/reg.shtml apart from sending the filled hardcopy of registration form. Spot-registration subject to availability at the after deadline rates against DD or Cash.
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