12th IEEE VLSI Design And Test Symposium
Advance Technical program
Keynote and Invited talks
VLSI Education Day
Teaching and Research in Microelctronics at IIT Bombay- A view from Lake Powai
Speaker: Arun N.Chandorkar, IIT Bombay
Arun N. Chandorkar is a Professor of Electrical Engineering at the Indian Institute of Technology, Bombay, India. He received the Ph.D. in Electrical Engineering in 1977 from Pilani. He worked at Tata Institute of Fundamental Research from 1978 to 1983, where he was a member of a group which was a poineer in developing India’s first 5 µm CMOS technology. Earlier, at both IIT Kanpur, and at CEERI, Pilani, he worked on Microwave Semiconductor devices, like Gunn diodes and S-band PIN diodes Currently his research interests include, VLSI Design (Digital,Analog and RF VLSI), VLSI Technology, Radiation effects in MOS devices and Circuits, Testing of VLSI systems, Optically Switched Microwave Semiconductor Components, Power Semiconductor Devices & Power Electronic Systems and Nanotechnology. He has contributed around 100 Technical papers in all the above areas.
In the last 25 years since his joining IIT Bombay, he has guided 18 Ph.D. students, 150 M.Tech. students and 80 B.Tech. students for their project work. He has been a Visiting Professor at EE Department of UCLA, and also at Tokyo Institute of Technology, Japan in 2006 where he is continuing the second time, and is engaged in advanced High-K dielectric research for sub 45nm CMOS technology.
He has been honoured with IIT Bombay’s prestigious Excellence in Teaching award in 1999, and the 6th IETE S.V.C.Aiyya award for his motivating research in Microelectronic Devices by the Institution of Electronics and Telecommunication Engineers, India. He was the General-Chair for 17th International conference on VLSI Design and 3rd International Conference on Embedded Systems held in Mumbai in January 2004.
He is a Fellow of IETE, Chairman IEEE EDS (Bombay Chapter), Vice President International Society of Reliability Engineers ( India Chapter ) and Senior Member of IEEE, and Fellow of Maharashtra Academy of Sciences.
VLSI Education Day
Analog and Mixed Signal Design – Need for a Curriculum Upgrade
Speaker: K.Radhakrishna Rao, Texas Instruments India
Abstract: Analog circuits are an integral part of a signal chain, since the environmental attributes that we wish to measure or control, such as ambient temperature, atmospheric pressure, relative humidity, etc., are analog in nature. This talk will look at what upgrades are needed in today’s curriculum to prepare the graduating engineer to the challenging task of designing, verifying, integrating, and testing analog circuits that are part of a system-on-chip.
K. Radhakrishna Rao is a Distinguished Member of Technical Staff (Emeritus) at TI India. He was with the Department of Electrical Engineering, IIT Madras, during 1971-2006 before he joined TI India. He obtained his Ph.D. (EE) from IIT Kanpur (1971) and B.Tech (EE) from IIT Madras (1966). His current interests are in analog IC design and continuous-time filters. He has taught Analog 101 (Introduction to Analog IC Design) and Analog 203 (Analog Filters) in PragaTI.
Enabling Systems on a Chip to Test Themselves
Speaker: Jacob A. Abraham, The University of Texas at Austin
Abstract: Advances in semiconductor technology have enabled the integration of digital,mixed-signal, and RF systems on a single chip. While Systems on a Chip (SoCs) offer many benefits in cost and performance, they pose significant challenges for testing after manufacture. This talk will describe a novel approach which uses the computational resources within the SoC to test itself. The embedded processor in the SoC can test itself by running instruction sequences from memory. The tests can target classic "stuck-at" faults as well as small delay defects which are becoming more common in scaled technologies. Techniques developed recently for generating instruction sequences which have very high coverage for path delay faults in the processor will be described.
The processor can then be used to test other cores in the SoC, including mixed-signal cores for analog and RF specifications. An approach to testing data converters by putting them in loopback mode will be described. On-chip sensors which can be used to test RF modules will also be discussed. Masurements have been performed on prototype hardware and integrated circuits, and results show that the approach can predict the specifications of the mixed-signal modules with high accuracy, enabling low-cost manufacturing test.
Jacob A. Abraham is Professor of Electrical and Computer Engineering and Professor of Computer Sciences at the University of Texas at Austin. He is also the director of the Computer Engineering Research Center and holds a Cockrell Family Regents Chair in Engineering. He received his Ph.D. in Electrical Engineering and Computer Science from Stanford University in 1974.
His research interests include VLSI design and test, formal verification, and fault-tolerant computing. He has published extensively and is included in a list of the most cited researchers in the world. He has supervised more than 70 Ph.D. dissertations, and is particularly proud of the accomplishments of his students, many of whom occupy senior positions in academia and industry.
He has served as associate editor of several IEEE Transactions, and as chair of the IEEE Computer Society Technical Committee on Fault-Tolerant Computing.
He has been elected Fellow of the IEEE as well as Fellow of the ACM, and is the recipient of the 2005 IEEE Emanuel R. Piore Award.
Electronic Design Evolution in India and its Impact on Semiconductor Design
Speaker: Sudip Nandy, Wipro Technologies
With the new dynamics increasing the need for companies to focus on technology domain expertise, systems understanding in addition to the challenges of doing design and the rising importance of verification at lower geometries, what are the next steps for the Indian semiconductor firms?
The electronic design ecosystem has been changing in India. With the faster growth of electronic product consumption and setup of more semiconductor design groups (both captive and non-captive), we see lot of demand and opportunities for local product creation. How does it impact the semiconductor development/engineering community? What are the new skills or capabilities that would be more important in this scenario?
Special session: Biomedical Electronics
Innovation Opportunities in Biomedical Electronics
Speaker: Shekar Rao, Worldwide Manager Medical Electronics Solutions, Texas Instruments Inc.
Abstract: New Opportunities for Biomedical Electronics System innovation exist and the intersections of Healthcare and IT; Medicine and IT; Biology and IT. The talk highlights the major clinical problems in the world, for which biomedical electronics and semiconductor chip solutions wil play an important role
Shekar Rao is the worldwide manager for medical electronics and healthcare solutions at Texas Instruments in Dallas, Texas. He is responsible for identifying centers of innovation in Medical Electronics Research in Universities worldwide and funding Research and Development activity. He possesses over 30 years of worldwide experience in product development, P&L, operations, business strategy, marketing, sales, and consulting within start-up as well as established companies such Texas Instruments, NEC Electronics and LSI Logic.
He has a track record in developing and implementing multi-product and multi-market business strategies. Mr. Rao is highly knowledgeable in anti-trust issues, intellectual property protection, patents and the promotion of industry-wide interoperability standards and collaborations. He has a deep understanding of issues and opportunities in industries as diverse as semiconductor, life sciences, healthcare, networking hardware, software, IT, knowledge management and workflow automation.
He is the Chair of the IEEE Engineering in Medicine and Biology Society Dallas Chapter.
Mr. Rao has a B.Tech.(EE with thesis in Biomedical Engineering) from IIT-Delhi, a Post Graduate Diploma (MBA) in International Trade from Indian Institute of Foreign Trade.
Special session: Biomedical Electronics
Connected Healthcare
Speaker: Dinesh Bhatia, Univ. of Texas at Dallas
Abstract: Recent advances in low power design and increasing demand for effective technology enabled solution for managing diseases as well as general health is resulting in pervasive patient monitoring solutions. This talk will introduce various solutions for disease management, continuous patient monitoring in hospital and home environments, as well as long term patient health record maintenance.
Dr.Dinesh Bhatia is on the faculty of electrical engineering department at The University of Texas at Dallas. He directs research activities within the Embedded and Adaptive Computing group and is also a member of Center for Integrated Circuits and Systems at the University of Texas at Dallas. His current research is focused on building solutions for patient monitoring technologies to provide effective medical care. His research interests also include all aspects of reconfigurable and adaptive computing, architecture and CAD for field programmable gate arrays (FPGAs), physical design automation of VLSI Systems, biomedical electronics and systems, medical devices, natural energy scavenging and, applications of wireless sensor networks. Some of his recent activities include principal designer and investigator for RACE and NEBULA systems for Wright Laboratories of USAF, principal investigator for DARPA funded REACT program, Co-PI on AFRL funded SPARCs program and several more.
He has collaborated on phase 1 and phase 2 SBIR programs to build product prototypes. He has published extensively in leading journals and conferences and continues to serve on program committees of several conferences. He is a senior member of IEEE, Computer Society, Circuits and Systems Society, Eta Kappa Nu, and recently served on the editorial board of IEEE Transactions on COMPUTERs. He is IEEE Circuits and Systems society’s distinguished lecturer for 2007-08.
Moving Event Localization using Multihop Cellular Sensor Networks
Speaker: Uday B. Desai, SPANN Lab, Dept of Electrical Engineering, IIT-Bombay
Abstract: The ubiquitous use of mobile phones motivates the idea of participatory sensing with a multihop cellular sensor network. In this talk we consider a moving event which is defined at any instant by the center of event (COE) occurrence and radius of influence (Re). The aim is to determine the trajectory of the moving event using sensed data obtained from mobile cell phone nodes that are located within the radius of influence. The data among cell phones is communicated in a multihop manner and not in the conventional centralized manner. On-the-fly aggregation and routing protocols are required for moving event localization using multi hop cellular sensor networks. The main contribution of this work is a novel Distributed Velocity-Dependent (DVD) Waiting Time based moving event localization protocol. In the proposed protocol, the duration (Waiting Time) for which a node needs to wait to receive data from other nodes for aggregation or relaying is determined from its local position and velocity. We also propose a Cluster-Head (CH) based moving event localization protocol, where a cluster head (CH) is elected in a distributed manner for each zone in a zonal architecture. We compare the proposed DVD and CH protocols with a modified Randomized Waiting (RW) time data aggregation protocol for moving event localization problem.
A brief mention will be made of other research, in the area of Multihop networks, pursued at SPANN Lab., IIT-Bombay.
Uday B. Desai received the B. Tech. degree from Indian Institute of Technology, Kanpur, India, in 1974, the M.S. degree from the State University of New York, Buffalo, in 1976, and the Ph.D. degree from The Johns Hopkins University, Baltimore, U.S.A., in 1979, all in Electrical Engineering.
From 1979 to 1984 he was an Assistant Professor in the Electrical Engineering Department at Washington State University, Pullman, WA, U.S.A., and an Associate Professor at the same place from 1984 to 1987. Since 1987 he has been a Professor in the Electrical Engineering Department at the IIT - Bombay. He was Dean Students at IIT-Bombay from Aug 2000 to July 2002. He has held Visiting positions at Arizona State University, Purdue University, Stanford University and EPFL, Lausanne. From July 2002 to June 2004 he was the Director of HP-IITM R and D Lab. at IIT-Madras.
His research interests are in wireless communication, wireless sensor networks and statistical signal processing. He is interested in connectivity for rural India.
Dr. Desai is a Fellow of INSA (Indian National Science Academy), Fellow of Indian National Academy of Engineering (INAE), and a Fellow of The Institution of Electronic & Telecommunication Engineers (IETE). He is on the (i) Executive Committee (EC) for the All India Council of Technical Education (AICTE). (ii) The Technical Advisory Board of Microsoft Research Lab. India. He is the IEEE Bombay Section Chair and a distinguished lecturer for IEEE Communication Society. He was on the Visitation panel for University of Ghana.
More information on him can be found at www.ee.iitb.ac.in/~ubdesai , www.ee.iitb.ac.in/~spann
Low Power Verification - overcoming the challenges
Speaker: Srikanth Jadcherla, Group Director R&D, Verification Group, Synopsys Inc.
Abstract: The advent of LP design brings forth an explosion in the verification space to cover : new power intent files, states, transitions, sequences etc. need to be verified in a productive and accurate manner. The tutorial will dwell into these changes in the context of verification flow. We will also look at topics for research for academia in this area briefly.
Srikanth Jadcherla came to Synopsys as part of the ArchPro acquisition, where he was founder and CTO. Prior to ArchPro, Jadcherla was an IC designer and architect at companies such as WSI, Intel, Jasmine and Synopsys. He is a veteran of low power designs and pioneer of many energy efficiency techniques and principles. Jadcherla received an Intel Achievement Award for his work on low power and is the author of 12 patents. He is an honorary green evangelist/technical advisor to various companies ranging from solar energy suppliers to real estate developers. Recently, he has been advocating new paradigms in energy efficient design in semiconductor systems worldwide from both the supply and demand side of energy consumption.
Jadcherla holds a bachelor’s degree in electrical engg from IIT-Madras in India, and a master’s degree in computational science and engg from the University of California, Santa Barbara.
System Verilog for VLSI design - prospects and challenges
Speaker: N.S. Murty, NXP Semiconductors
Abstract: As designs grow in size and complexity, the challenges associated with the growing design and verification gap have created the need for a paradigm shift in the IP and SoC design and verification methodology from the traditional approaches. SystemVerilog provides a number of advantages including design specification at a higher abstraction level, code reuse and unified design and verification. Its advanced design constructs yield more compact RTL code, typically a two-to-four times reduction in the RTL lines thereby reducing coding errors and increasing the design productivity.
SystemVerilog achieves improved design specification describing more functionality using less lines of code. This is done by allowing the related functionality to be described as a single object. SystemVerilog constructs allow the designers to express the intent clearly in a way the simulation and synthesis tools can have a unified view of the RTL. Assertions in SystemVerilog can be used to specify and validate the design behavior. This presentation will highlight the benefits of using SystemVerilog for design through a reference design as case study.
Dr. N.S.Murty is the Director, Technology Management of NXP Semiconductors India. In this role, he drives NXP’s technology roadmaps, innovation, technical competencies, knowledge management and academic relations program. Before taking up this role, he was the manager of the Reuse Technology Group in Chief Technology Office, overseeing the design and development of HW, SW and integrated IPs and subsystems. He has been with NXP and Philips Semiconductors for 7 and half years; and prior to joining Philips, he was with IBM as general manager of VLSI design team.
He obtained Ph.D. in Microelectronics from Electrical Engineering Dept of IIT Bombay, and MBA from IGNOU, Delhi. He has about 25 years of industrial experience in VLSI and systems design, manufacturing, reliability testing and failure analysis in several capacities. He has more than 30 publications/presentations in microelectronics in international journals/conferences.
Physical design EDA challenges for 32nm and beyond
Speaker: Mysore Sriram, Intel
Abstract: With the 32nm era fast approaching, new challenges to EDA tools are surfacing, especially in the physical design arena. Several process trends become critical at this process node, such as interconnect scaling, layout design rules and statistical variability. Each of these trends has significant implications for EDA tools. Interconnect scaling, and the resultant exponential increase in the need for repeaters, causes major issues for logic synthesis, standard cell placement and chip-level integration. The complexity of new OPC-friendly layout design rules has profound impact on routing algorithms, and stresses the need for manufacturing awareness earlier in the design process. Similarly, manufacturing-induced variability necessitates more robust clock distribution approaches and statistical design concepts built into EDA tools to prevent excessive guardbanding. This talk will explore some of these themes and current research in these areas.
Mysore Sriram is a Principal Engineer at Intel. Over 15 years at Intel, Sriram has worked on CAD tool development, and physical integration of multiple generations of server CPU designs. His research interests are in the areas of physical design, optimization algorithms and interconnect design. He holds three US patents, and is the co-author of a book and several research papers on physical design. Sriram has a B. Tech from IIT Madras, and an MS and Ph.D. from the University of Illinois at Urbana Champaign.
Design Methodology for a 2.5GHz Native Quad Core x86 Processor
Speaker: Prasad Kuppa, AMD
Abstract: Microprocessor innovation is at crossroads. Relentless push towards frequency as a single vector has imposed challenging design constraints and cost. In this talk we will discuss about Soc challenges of designing multi-core processors and correct by construction methodology to address GHz designs with considerations to improving perf/watt (Power efficiency).
Topic : TBA
Speaker: Jayanta Lahiri, ARM Embedded Technologies
Abstract: TBA