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Papers Selected For the Symposium

The results of paper selection/review for VDAT 2005 event are published here.

If your paper was not selected for inclusion, please accept our sincere regrets. Kindly note that we received about 150 submissions to VDAT 2005 this year and keeping in mind the limited time available for paper presentations, we had to reject several good papers.  Please do read the comments in reviews to further improve your paper and consider submitting it to an alternate forum.  We hope you will continue your patronage of VDAT.

The Program Committee congratulates the authors of papers that have been included in the technical program.  If your paper has been selected, please go through the 'Information for Authors' carefully.

The final selection includes 16 full papers, 26 short papers, and 22 posters. 

 

Decision of the Program Committee

The list of papers selected for VDAT 2005 Symposium is given below:

Paper Title Category
4170 Mixed design of Self-Timed Logic in Synchronous Systems Tutorial
4016 Design and FPGA Implementation of Wavepipelined Image Block Encoders using 2D-DWT Regular Paper
4083 Factoring Large Numbers using FPGA Short Paper
4068 FPGA Implementation Of Soft Decision Viterbi Decoder Short Paper
4114 Low Power Techniques for CMOS Designs Tutorial
4136 Glitch-Free Design of Low Power ASICs using Customized Resistive Feedthrough Cells Short Paper
4130 A 1.2V Low Power CMOS Bulk Driven Operational Amplifier Short Paper
4066 Online Adaptive Power Management for Non-Stationary Service Request Regular Paper
4021 Multi-level Current-mode Signaling for Long High-Speed Interconnects Regular Paper
4014 Boundary Fair Round-Robin: A Fast Fair Scheduler Regular Paper
4019 UML based Object Oriented Methodology for Analog Test Structure Design Automation Short Paper
4013 An Optimal Algorithm for Register Renaming: A Post Compilation Technique Short Paper
4040 Nanoscale design of Low power Supply Pseudo Resistive Cascode Current Mirror Short Paper
4027 Verilog -A Modeling of Parasitic and Biasing effects in PSRR behavior of Brokaw Bandgap Voltage Reference Short Paper
4146 Low Voltage Current Mode Pipelined 10MS/s Analog to Digital Converter Short Paper
4092 Petri Net Modeling of GALS and Implementation in Baseband Datapath component of an IEEE 802.11a compliant modem Short Paper
4041 Design and Simulation of Host Controller Interface for USB with Powered HUB Short Paper
4007 Real-Time Image Processing System Short Paper
4165 Partial and Dynamic Reconfiguration in Xilinx FPGAs – A Quantitative Study Short Paper
4142 Dynamic Reconfigurable Architecture for Blowfish Encryption using Inner Loop Pipeling, Loop-folding Techniques Short Paper
4103 Programmable Galois Multiplier Using Cellular Automaton Short Paper
4089 CMOS SRAM Fault Detection Using Dynamic Power Supply Current Poster Paper
4116 Energy-Performance Improvement of Content Addressable Memory by Dual-Threshold CMOS Technology Poster Paper
4062 Evolving Cellular Automata for Low power Testing of Circuits Poster Paper
4006 Integrated Core and Interconnect Testing with Test-time and Scan Power Minimization Poster Paper
4028 Comparative performance of Logic Synthesis Objectives in FPGA Design Flow Poster Paper
4026 Synthesis of Multiple-Valued Arithmetic Functions using Evolutionary Process Poster Paper
4025 Enabling ESL Design Through Behavioral Synthesis Poster Paper
4067 Omura’s Modular Addition for FPGA Implementation of the IDEA Cipher Block Poster Paper
4005 Performance optimized VLSI Implementation of RC5 Encryption Algorithm Poster Paper
4139 FPGA Implementation of OFDM WLAN Modem Poster Paper
4075 Diagnostic Testing of Memories for Static and Dynamic Faults Regular Paper
4125 Test Plan Coverage by Formal Property Verification Regular Paper
4063 An Integrated Computer Aided Test (CAT) Tool for System on Chip Short Paper
4085 On-Line BIST for Testing of Operational Amplifiers Short Paper
4152 Area Optimization Tips in Memo Regular Paper
4168 A Novel Random Access Scan Flip-Flop Design Regular Paper
4064 An Accurate Critical Path Based Characterization Scheme for Memory Compilers Short Paper
4118 A Hybrid System Approach to Failure Diagnosis of Analog VLSI Circuits: A Case Study of DC-DC Buck Converters Regular Paper
4164 A technique for predicting the effect of Data Cache Associativity Short Paper
4159 On ways to improve the Adaptive Filter Technique using Verilog HDL and CPLD Short Paper
4159 On ways to improve the Adaptive Filter Technique using Verilog HDL and CPLD Short Paper
4180 Probabilistic Error Model for Unreliable Nano-logic Gates Regular Paper
4060 SAST : An Interconnection Aware High-level Synthesis Tool Short Paper
4077 Bounded Model Checking for Open LTL Short Paper
4126 Syntax-driven Approximate Coverage Analysis for an Assertion Suite against a High-level Fault Model Regular Paper
4157 Effect of Timing Jitter on High Speed Data Converter System Short Paper
4039 Synthesis and Testing of Reversible Logic – A Survey Tutorial
4171 Testing methods, Parameters an Tutorial
4104 ANN Implementation for Hearing Aid Noise Recognizer Poster Paper
4038 A Generic Time Division Duplex Scheme for Synchronous Traffic and Control of Remote Communication Devices Poster Paper
4022 VHDL Model of a Cognitive System for Telemedicine Applications Poster Paper
4012 A Universal Logic for Quantum-Dot Cellular Automata Poster Paper
4031 Domino Logic with Variable Body Biased Keeper Poster Paper
4111 Efficient Energy Recovery Technique for Positive Feedback Adiabatic Logic Poster Paper
4105 Extraction of Gate Tunneling Current in Gaussian Doped High-k Ultra-Thin-Body Double Gate (DG) MOSFET Poster Paper
4166 Compact Low Voltage VHF Continuous –Time Current Mode Filters Based on First Order Low-Pass Building Blocks Poster Paper
4112 An Adaptive Algorithm for power management at system level Poster Paper
4053 Crosstalk aware Line Search Algorithm for Analog Routing Poster Paper
4091 A Novel Bus Coding Technique for Low Power Data Transmission Poster Paper
4163 Search Space Pruning for Faster Test Generation based on Parallel and Adaptive GA Poster Paper
4011 A 16-bit, 200uA, 10us, Monotonic D/A Converter in SOT-23 package Short Paper
4153 Design and Implementation of Class AB CMOS Power Amplifier using GSMC 0.15u Technology Short Paper
4167 Independence Fault Collapsing Short Paper