Advance Program
VLSI Design and Test Workshops 1999
August 20-21, 1999
New Delhi, India

Click here to see Proceedings

Scope: To promote applications and research related to all aspects of VLSI

Sponsors: VLSI Society of India, IEEE Computer Society Technical Council on Test Technology and IEEE Computer Society Technical Committee onVLSI.
With Support From: Indian Institute of Technology, Delhi; Cadence India; Philips Semiconductors, India; Texas Instruments, India

Venue : The Habitat World, Lodi Road, New Delhi 110003

Click to see the Registration Form
Advance Program for August 20, 1999 (Friday)

Time

Test Workshop

Chair: C.P. Ravikumar

Room: Silver Oak II

Logic Design Workshop

Chair: Anshul Kumar

Room: Willow

Physical Design Workshop

Chair: Bhargab B. Bhattacharya

Room: Magnolia
8:30 to 9:30 AM
Registration
Registration
Registration
Session T1
Topics in Testing
Chair : TBA
Session P1
Layout Optimization
Chair: TBA
9:30 to 10:00 AM Prabir Dasgupta, Santau Chattopadhyay and I. Sengupta, IIT Kharagpur,Test Sequence Generation with Cellular Automata, S. Sahni. University of Florida. Efficient Algorithm for the Channel Inversion Problem.
10:00 to 10:30 AM Amit Premy, Texas Instruments, India. Test Simulation Flow for Mixed Signal ICs. Parthasarathi DasGupta, Indian Institute of Management. Complex Triangle Elimination Problem and its Applications to VLSI.
10:30 to 11:00 AM M.C. Bhuvaneshwari and S.N. Shivanandam, PSG College of Technology. Testing of Asynchronous Circuits. Dinesh Bhatia, University of Cincinnati. OH, USA.Layout Algorithms for FPGA.
11:00 to 11:30 PM
Tea Break
Tea Break
Tea Break


Time
Session T2
Design for Testability
Chair: TBA
Session L1
VLSI Design Processes
Chair: TBA
Session P2
Signal Integrity I
Chair: TBA
11:30 to 12:00 PM T. Ramesh, Philips Semiconductors, Bangalore, India. Design for Testability Issues. in VLSI Chip Design Susheel Sinha, Texas Instruments, Bangalore, india. Managing VLSI Design Complexity: Lessons from Software Experience. (Invited Talk)
12:00 to 12:30 PM A.Bagwe and Rubin Parekhji, Texas Instruments, Bangalore, India. Techniques for Improving Fault Coverage in Embedded Core Based Systems. Vineet Sahula, IIT Delhi. Extended Signal Flow Graph Model for VLSI Design Processes. S. Sankara Subramanian, ATI Tech, G. Rajagopalan, Analog Devices, and C.P. Ravikumar, IIT Delhi. Crosstalk Estimation in VLSI Circuits.
12:30 to 1:00 PM Srikanth Balasubramanian, Philips Semiconductors, Bangalore, India. Testing Memory Designs. V. Srisha and Saif Khan, Philips Semiconductors, Bangalore, India. System-level VLSI Design Experiences.
1:00 to 2:00 PM
Lunch
Lunch
Lunch

Session T3

Analog Testing

Session L2

Timing Closure

Session P3

Graph Theory
2:00 to 4:00 PM V.C. Prasad, IIT Delhi. Tutorial on Analog Testing. (Invited) Hemendra Godbole, Synopsys, USA. Tutorial on Timing Closure in System on Chip Designs. (Invited) Rubin Parekhji, Texas Instruments (India) Ltd. Tutorial on Applications of Graph Theory to VLSI Design Problems. (Invited)
4:00 to 4.30 PM
Tea Break
Tea Break
Tea Break
4.30 PM to 6.00 PM Panel Discussion: The Present and Future of VLSI in India The panel will discuss the problems that presently face the VLSI industries in India. The panel will also try to debate on the future of VLSI in India. The names of panelists will be announced later.


Advance Program for August 21, 1999 (Saturday)

Time

Test Workshop

Room: Silver Oak II

Logic Design Workshop

Room: Willow

Physical Design Workshop

Room: Magnolia

Session T4

Verification I

Session P4

FPGA Layout
9:00 to 11:00 AM Ranga Vemuri, University of Cincinnati. Tutorial on Verification of Synthesized RTL Designs. (Invited) Dinesh Bhatia, University of Cincinnati, OH, USA. Ultra-Fast Placement for FPGAs (Invited)
11:00 to 11:30 AM
Tea Break
Tea Break
Tea Break
Session T5
Verification II
Session L3
Memory Design
Chair: Rajamohan Varambally
Session P5
Optimization
11:30 to 12:00 AM Apurva Kalia, Cadence Design Systems, Noida, India. Tutorial on Verification of VLSI Systems. (Invited) B. Suresh and Harinath, Texas Instruments (India) Ltd. RTL Design of a Small Memory Ganesh Kamath and Preetham Kumar, Texas Instruments (India) Ltd., A Physical Layout Efficiency Checker with an Emhpasis on Die Area Reduction
12:00 to 12:30PM R. Varambally and Christophe Frey, ST Microelectronics. Design and Results of a Hierarchical Megabit SRAM Compiler. Rupesh S. Shelar, Silicon Automation Systems, Madhav Desai and H. Narayanan, IIT Bombay. Decomposition of Finite State Machines for Area, Delay Minimization.
12:30 to 1:00 PM G. Sreenivas, Cypress Semiconductors. Power-constrained Testing of Embedded SRAMs. Shampa Chakraverty, Netaji Subhash Institute of Technology, Estimating the Deadline Miss Probability in Real Time Embedded Systems.
1:00 to 2:00 PM
Lunch
Lunch
Lunch
Session T6
New Ideas in Testing
Session L4
Low-Power Digital Signal Processing
2.00 to 2.30 PM Gaurav Chandra, Ashutosh Verma, C.P. Ravikumar, IIT Delhi. Power-constrained Optimization of Test Plans. Mahesh Mehendale, Texas Instruments (India) Ltd. A Methodology for Exploring Area-Delay-Power Space for DSP
2.30 to 3.00 PM Prabir Dasgupta, Santanu Chattopadhyay, I. Sengupta, IIT Kharagpur. Recursive Pseudoexhaustive Test Pattern Generation with Cellular Automata. Amitabh Menon, Texas Instruments (India) Ltd. Low Power Microarchitectures for Programmable DSPs.
3.00 to 3.30 PM N.Prasad, J.Abraham and R.A.Parekhji, Texas Instruments, India. Design Tradeoffs for Test of Embedded Cores. S.D. Sherlekar, Silicon Automation Systems. System Level Considerations in Realizing Low Power DSP Applications.
3.30 to 4.00 PM
Tea
Tea
Tea
Session T7
Verification III
Session L5
Design Ideas
Session P6
Signal Integrity II
4.00 to 4.30 PM Anand Hardi, Anil Kalra , Balwant Singh , Santosh and Shamsi Azmi, ST Microelectronics. On-chip characterization and Debugging methodology for high-speed embedded memories. Rohit Sharma, Texas Instruments (India) Ltd. Area-Efficient Digital Waveform Generators. Sabyasachi Nag and Ananth Somayaji, Texas Instruments (India) Ltd. An approach towards Hierarchical Detection of ESD Errors in a Physical Layout.
4.30 to 5.00 PM Rubin Parekhji, Texas Instruments (India) Ltd. Processor Emulation Design and Verification. Anil K. Gundurao and Kaushal, Cypress Semiconductors. Clock Generator Chip: Architecture/Design Issues. C. Rajkumar and Sanjay Kulkarni, Texas Instruments (India) Ltd. An Effective Methodology to Extract Parasitic from Layout.
5.00 to 5.30 PM Hafijur Rahaman, Debesh K. Das, and Bhargab B. Bhattacharya. A BIST for Detecting Multiple Stuck-open and Delay Faults by Transition Counts Pradeep Mandal, Philips Semiconductors, Bangalore, India. I/O Pad Design.

Program Chairs for the Workshops

Technical Program Committee

Registration Information:
Registration permits you to participate in all the technical sessions and tutorials organized as part of the workshops. Refreshments and lunch will be provided to all registrants at no extra charge. Please send your registration fee through a draft made out to VLSI Design and Test Workshops, 1999. Make the draft payable at Canara Bank, IIT Delhi Hauz Khas Branch. The draft must be sent to Dr. C.P. Ravikumar, Department of Electrical Engineering, Indian Institute of Technology, New Delhi, 110016, India. If you wish to register on the spot, drafts and cash payment in Indian rupees are acceptable. We will not be able to accept Foreign Currency or Credit Card payments. The current exchange rate is approximately 1 US dollar = 45 Indian rupees.

Registration Fees Before July 20, 1999
Indian Participant Foreign Participant
Academic Institution
Rs. 2000
USD. 50
Non-academic Institution
Rs. 4000
USD. 150
Registration Fees After July 20, 1999
Indian Participant Foreign Participant
Academic Institution
Rs. 2500
USD. 75
Non-academic Institution
Rs. 4500
USD. 175

Venue Information:Contact numbers for The Habitat World are:+91 11 469-1920 and +91 11 469-1921. FAX number is +91 11 460-2118. Please ask for Ms Aarti Bhargava when inquiring about the workshops. There are several Web sites that will give you information about travel and stay in New Delhi, including www.delhizone.com. A map showing the location of Habitat World in New Delhi is available at www.iiefair.com/habitatmap.html . Habitat World is located at Lodi Road, New Delhi and a pre-paid taxi from the air port to a hotel around this area will cost Rs. 150 (About 4 US Dollars). You must enter from Gate 2. Prepaid taxis can be purchased at the airport itself. Tipping the taxi driver is not necessary. Alternative accommodation may be available in guest houses of organizations within New Delhi; you must contact the organizing chair before Aug 1, 1999 regarding this.

Weather Information:The weather in New Delhi in August is hot (temperatures ranging in 30 degrees to 35 degrees centigrade), with inermittent rain. Umbrellas are recommended.

Contact Information:In case you have any questions, please contact C.P. Ravikumar (rkumar@ee.iitd.ernet.in) for clarifications. E-mail can also be sent to vdat99@hotmail.com.

Student Participation:A small number of full or partial waiver of registration fee is available for Indian students and Indian faculty. Preference will be given to attendees who request for partial waiver. Write to the organizing chair with a statement of purpose for attending the workshops before July 20, 1999. Please note that travel support and staying arrangements will have to be made by the participant who avails the free registration.

Thanks to :
Rohit Sharma of Texas Instruments, India has provided invaluable help in compiling the abstracts for publication on the Internet.He has also helped me immensely with the maintenance of vdat@egroups.com

Some related sites : 12th International Conference on VLSI Design, Goa, India, 1999
VLSI Design and Test Workshops, January 1998