VLSI Design and Test Workshops
August 20-21, 1999
New Delhi, India.



 
Test Worksops
    1. Santau Chattopadhyay et. al., IIT Kharagpur. Test Sequence Generation with Cellular Automata.
    2. Amit Premy, Texas Instruments, India. Test Simulation Flow for Mixed Signal ICs.
    3. M.C. Bhuvaneshwari. Testing of Asynchronous Circuits.
    4. T. Ramesh, Philips Semiconductors, Bangalore, India. Design for Testability Issues in VLSI Chip Design.
    5. Rubin Parekhji, Texas Instruments, Bangalore, India. Techniques for obtaining higher fault coverage.
    6. Srikanth Balasubramanian, Philips Semiconductors, Bangalore, India. Testing Memory Designs.
    7. V.C. Prasad, IIT Delhi. Tutorial on Analog Testing. (Invited)
    8. Ranga Vemuri, University of Cincinnati. Tutorial on Verification of Synthesized RTL Designs. (Invited)
    9. Apurva Kalia, Cadence Design Systems, Noida, India. Tutorial on Verification of VLSI Systems. (Invited)
    10. Gaurav Chandra, Ashutosh Verma, C.P. Ravikumar, IIT Delhi. Power-constrained Optimization of Test Plans.
    11. Prabir Dasgupta et al., IIT Kharagpur. Recursive Pseudoexhaustive Test Pattern Generation with Cellular Automata.
    12. R. Parekhji, Texas Instruments, Bangalore, India. Issues in Testing Core-based Systems.
    13. Anand Hardi, Anil Kalra , Balwant Singh , Santosh and Shamsi Azmi, ST Microelectronics. On-chip characterization and Debugging methodology for high-speed embedded memories.
    14. Rubin Parekhji, Texas Instruments (India) Ltd. Emulation as a verification tool.
    15. Prabir Dasgupta, Santanu Chattopadhyay, and Indranil Sengupta, IIT Kharagpur. Recursive Pseudoexhaustive Test Pattern Generation with Cellular Automata.
 
Logic Design Worksops
    1. Susheel Sinha, Texas Instruments, Bangalore, india. Managing VLSI Design Complexity: Lessons from Software Experience. (Invited Talk)
    2. Vineet Sahula, IIT Delhi. Extended Signal Flow Graph Model for VLSI Design Processes.
    3. V. Srisha and Saif Khan, Philips Semiconductors, Bangalore, India. System-level VLSI Design Experiences.
    4. Hemendra Godbole, Synopsys, USA. Tutorial on Timing Closure in System on Chip Designs. (Invited)
    5. B. Suresh and R. Harinath, Texas Instruments (India) Ltd. RTL Design of a Small Memory.
    6. R. Varambally and Christophe Frey, ST Microelectronics. Design and Results of a Hierarchical Megabit SRAM Compiler.
    7. G. Sreenivas, Cypress Semiconductors. Power-constrained Testing of Embedded SRAMs.
    8. Mahesh Mehendale, Texas Instruments (India) Ltd. A Methodology for Exploring Area-Delay-Power Space for DSP
    9. Amitabh Menon, Texas Instruments (India) Ltd. Low Power Microarchitectures for Programmable DSPs.
    10. S.D. Sherlekar, Silicon Automation Systems. System Level Considerations in Realizing Low Power DSP Applications.
    11. Rohit Sharma, Texas Instruments (India) Ltd. Area-Efficient Digital Waveform Generators.
    12. Anil K. Gundurao and Kaushal, Cypress Semiconductors. Clock Generator Chip: Architecture/Design Issues.
    13. Pradeep Mandal, Philips Semiconductors, Bangalore, India. I/O Pad Design.
 
Physical Design Worksops
    1. S. Sahni. University of Florida. Efficient Algorithm for the Channel Inversion Problem.
    2. Parthasarathi DasGupta, Indian Statistical Institute. Complex Triangle Elimination Problem and its Applications to VLSI.
    3. Dinesh Bhatia, University of Cincinnati. Layout Algorithms for FPGA.
    4. S. Sankara Subramanian, ATI Tech, G. Rajagopalan, Analog Devices, and C.P. Ravikumar, IIT Delhi. Crosstalk Estimation in VLSI Circuits.
    5. Rubin Parekhji, Texas Instruments (India) Ltd. Tutorial on Applications of Graph Theory to VLSI Design Problems. (Invited)
    6. Dinesh Bhatia, University of Cincinnati. Tutorial on FPGA Layout. (Invited)
    7. Ganesh Kamath and Preetham Kumar, Texas Instruments (India) Ltd. A Physical Layout Efficiency Checker with an Emhpasis on Die Area Reduction.
    8. Rupesh S. Shelar, Silicon Automation Systems, Madhav Desai and H. Narayanan, IIT Bombay. Decomposition of Finite State Machines for Area, Delay Minimization.
    9. Shampa Chakraverty, Netaji Subhash Institute of Technology. Estimating the Deadline Miss Probability in Real Time Embedded Systems.
    10. Sabyasachi Nag and Ananth Somayaji, Texas Instruments (India) Ltd. An approach towards Hierarchical Detection of ESD Errors in a Physical Layout.
    11. C. Rajkumar and Sanjay Kulkarni, Texas Instruments (India) Ltd. An Effective Methodology to Extract Parasitic from Layout.