The team's methodology was based on analog backtrace, a technique that uses analog blocks themselves to test digital blocks. The methodology stresses the controllability of the inputs of the digital block by exploiting the analog block.

In a paper presented in the VLSI Design and Test 2007 held here, the team said its results were based on work done at the transfer function level. However, transistor-level simulation of analog circuits must be performed for a more realistic study, and it is on this aspect that the team is now working, the researchers said.

The investigators contend that, although problems in automatic testing and test pattern generation for digital circuits have been solved, directly applying and observing test patterns and responses is not possible when digital blocks are embedded in between analog blocks, as in mixed-signal ICs.

The team developed a methodology that enables it to exploit the analog circuits themselves to test embedded digital blocks with as little overhead as possible. They addressed the first problem in testing digital modules in mixed-signal circuits (treating the analog blocks as ideal). Next, parameter variations in the analog block were considered for developing an effective test solution. The effectiveness of the technque were verified by simulation of some analog benchmark circuits.

"Recent improvement in fabrication technology has made possible the realization of ICs containing both analog and digital functions on the same silicon. The problem of testing digital cores in the circuits is, however, more complicated than that of testing purely digital cores," the researchers said.

Because the analog blocks have direct access to the digital cores through quantizers, and because the team controlled the analog block directly, discrete Fourier transform overheads were minimized, the researchers said. "Our proposed test methodology emphasizes the controllability of the input of the digital block by exploiting the analog block."

The new program will focus on developing four streams of engineering manpower to meet growing demand for design engineers from technology companies expanding here. New VLSI design labs with advanced EDA tools are also planned.

The first stream will focus on doctorate-level VLSI design and related software development. The next will look at generating post-graduate engineers in VLSI design and microelectronics. A third will boost the number of post-graduate engineers in electronics and computer science with VLSI design as an elective subject. Finally, a program will provide graduate engineers with exposure to VLSI design, according to India's Ministry of Information Technology.

"The framework can be used to generate directed test for functional verification of processors, at different levels, namely, the Instruction Set Architecture to Micro-architecture, and also combinations of them," the paper said. "A constraint solver-based approach is employed in the framework. The effectiveness of the framework is demonstrated by developing the same using the ILOG Constraint Solver and plugging-in Cache and Translation Look-aside Buffer (TLB) models into it," the paper added.

One benefit of the framework is the plug-and-remove feature it offers for different modules, useful for evolving designs where design development and verification are done concurrently, the paper said.

Shibaji Banerjee and Dipanwita Roy Chowdhury of the Indian Institute of Technology, Kharagpur, have developed a new test strategy algorithm to exploit the possible parallelism of testing the cores. The algorithm generates the needed TAM switches, the configuration information of all the TAM switches and also TAM-to-Core connection need for the SoC under test.

A new computer aided test (CAT) tool has also been developed to test the SoC designs, they said.

In a sequential core, only scan chains are considered for testing as flip flops are more defect prone, so no extra hardware except the TAM switch is needed for the test. The benefit of considering only scan chains is that they can be tested in parallel. The test access mechanism is implemented on-chip by using a special TAM switch, and a synthesizable RTL core can be instantiated in a design to provide test access data to embedded cores in the SoC.

The TAM switch is a programmable cross bar switch allowing efficient delivery of test vectors to embedded cores at varying bandwidth. It has two useful operational modes-- in the cross configuration the switch is configured to send the test patterns to the core-under-test. while in the pass configuration the switch passes the test patterns to the next switch.

The proposed scheduling algorithm is divided into that for sequential cores in the SoC, another for combinational cores in the SoC and a third for the SoC with both sequential and combinational cores. During scheduling, the higher priority nodes are scheduled first, based on lower label nodes having higher priority than those with higher labels, while among nodes having the same label nodes with higher weight get priority.

The ISA also continued its push to expand engineering education. The organization unveiled its University Gateway Initiative in partnership with the VLSI Society of India (VSI).

The ISA also signed a memorandum of understanding agreement with the regional body for engineering education, the Visvesvaraya Technological University (VTU).

The VTU oversees Karnataka state’s engineering education, including Bangalore, the state capital, and with 120 institutes. This deal is expected to propel recruitment for the growing design services industry in the country.

“Talent generation is central to the Indian semiconductor industry’s effort to move up the value chain and gain global eminence. In our industry, a clear way for achieving this is through a ground initiative that encompasses every facet and fosters the creation of a supportive ecosystem. With this initiative, ISA has taken the lead in making it happen,” said Rajendra Kumar Khare, chairman of the ISA.

A survey by the group has found that that less than 1,000 students graduating with bachelor's degrees annually specialize in semiconductors/VLSI.

This means that less than one percent of graduating engineers in India have the skills the design services industry here needs. That such skills here are rare is no secret, but this is among the first surveys by an industry body, which also indicated that less than 500 master’s degree students come out annually with the necessary skills.

In the inaugural issue of the Society's newsletter, Bobby Mitra, president, VLSI Society of India and head of Texas Instruments (India) Pvt. Ltd., said a large pool of highly skilled individuals is needed to execute the increasing number of chip design projects coming to India.

"This is an area of concern for us all. How do we grow and sustain the adequate number of highly talented people to take this revolution forward?" he asked.

The number of graduates interviewed by managers before hiring one is staggering-- sometimes as high as 30. "This speaks volumes about the gap in the expectations of the industry and the output coming from academic institutions," said C.P. Ravikumar, senior technologist, Texas Instruments.

Managers' complaints range from interviewees being weak in basic concepts, inability to answer simple questions about electrical circuits and digital logic. Besides, technical institutes do not have the resources to recruit faculty, develop labs and invest in software tools. Some institutes either have no courses in semiconductor devices, circuit design and test or make these optional for students, most of whom prefer a job in application software development.

Some faculty believe CMOS circuit design, design flows, effect of interconnects, design timing, verification and testing need to be stressed. Industry appears apathetic, interested only in fresh hires, and not interacting with institutes, offering internships, student projects or research funding.

While popular tools and subflows are available, no single framework exists, the team said in a paper at the VLSI Design and Test (VDAT) 2003 meeting here recently. Their solution is targeted for now on the physical-design aspects of VLSI but the concepts are generic and can be applied to front-end or other design flow segments as well. Abhishek Pandey, Pradeep Cavale and A. Krupakaran of Spike Infotech in Bangalore said their solution, QuickFlow (QF), provides a seamless flow to take a design from RTL to GDSII by allowing the creation of flows based on a mix of preferred tools. QuickFlow allows for efficient utilization of resources such as servers and licenses, and captures reuse within the system, the trio said.

"QF is easily customizable to new and emerging technologies like 0.13/0.09 micron and above, and to specific foundries. An expert-system-based learning is available to help users choose tools/flows for their specific purposes and project management capability is included within the system. All these features come with a Web-based control to the system for initiating and monitoring tasks. The scope for future work includes improving the learning capabilities of such a system," their paper said.

Finding from their customers that there is need for such a system as QF, the engineers said the benefits it brings are immense. QF addresses the needs of rapid design flow creation and management, archiving of reusable design flows, capture of tool/flow expertise within the system, design flow execution control and full-time monitoring of the status of design flow runs. Status information is available to designers from the flow, which is said to monitor hardware and software resources and to offer effective project management.

Growing database
The QF environment is one that enables users to create and maintain a design flow with a knowledge database that grows over time. This environment controls flow execution and other aspects of typical physical-design projects. QF is billed as a fully configurable and customizable solution, in which the quality is dependent on the designers doing the configuration.

QF is accessible from anywhere through the Internet, and a built-in messenger communicates with designers by e-mail to keep them updated on the status of the flow execution. It addresses security concerns of some Web-based systems by using the Secure Sockets Layer and Message Digest 5 for encryption. It has multi-tier user management for improved project control supporting administration, managerial and designer user types.

The knowledge database, called CookBook, contains tool recipes, and is reusable across projects, since it is generic. Designers can create a flow by using recipes in the CookBook, the team said.

The system performs status monitoring of task execution, with output of tasks viewed through a Web page. When an execution is finished, an e-mail goes out to the designer with the return status. All involved can monitor project status too, the designers said. QF can also be configured to add more intelligence to the system with plug-in scripts; a scripting language has been developed for this.

QF makes it possible to distribute jobs on different servers to keep the load optimal, the three engineers said. Enhancement also ensures that the program addresses concerns of tool licenses and allows tracking of versions of design files. Metrics can also be provided to review design projects, including time spent on tasks, designer productivity and number of iterations for different branches in a flow.

Case studies indicated that QF reduces design time, the paper said, and more reductions are expected over time. QF has been used on small and medium-size designs and is being benchmarked on million-gate designs. It is now being deployed on a 0.13-micron design.

Elsewhere at VDAT, two professors at an engineering college in Coimbatore in southern India have proposed a new VLSI design for an existing routing algorithm using a parallel architecture. K. Paramasivam and K. Gunavathi said simulations showed that results obtained by using the new design prove that a routing table can be created with optimized and suboptimal paths based on reliability studies for nodes as well as the path. The pair said in their paper that while they implemented and simulated using a 17-node communication network, the simulation could be extended for larger networks with more nodes as well.

In another paper, K. Gunavathi and H. Mangalam presented a theory and algorithms for building a low-power clock tree using two low-power clock schemes: reduced swing and multiple supply voltages. New ways to cut power dissipation are needed, since the clock network can dissipate 20 to 50 percent of the total power on a chip. Ignoring static power dissipation in their study, the pair controlled short-circuit power dissipation by enforcing a constraint that the clock edge should never have a transition (rise/fall) time that is larger than a given specification throughout the clock tree. "By enforcing this sharp clock requirement, the short-circuit power is bounded and can be neglected in comparison with the charge/ discharge power," they said.

The proposed algorithm for clock tree distribution is similar to previous work in many ways, Gunavathi and Mangalam said, except that it uses an HL converter at the root of the tree and an LH converter at various points in the clock tree. Tests showed power savings of an average of 45 percent are possible for a 0.25-micron technology using multiple supply voltages and about 32 percent using a single external supply voltage, they said.

Smarter tools
Also at VDAT, Bedanta Choudhury of STMicroelectronics India juxtaposed design-for-manufacturability (DFM) needs against design-specific requirements involved in creating standard cells, the basic building blocks of analog and digital circuits. An intelligent compromise can be made by fusing design expertise with manufacturing-process expertise, he said. The paper discussed ways to make CAD and design tools DFM-intelligent to achieve higher semiconductor reliability. It said that while leading EDA companies have launched some promising tools in the market, there is much more scope for R&D in DFM-smart EDA.

Engineers at Texas Instruments India presented a method for achieving predictability in crosstalk noise analysis and closure by identifying the real- and root-cause noise problems needing to be fixed so that new violations are not discovered after repair. Their method aims at reducing pessimism in the analysis by using data arrival times and "slack" information, and draws a relationship between the timing slack and glitch criticality. The TI team discussed gaps in hierarchical crosstalk analysis methods and presented a flow to fill those gaps.

Another paper described a methodology based on a parameterized analog cell library to automate analog design. One paper found that the results from testing both the cores and the interconnects between them in systems-on-chip were better than when the cores and interconnects were considered separately.