14th VLSI Design And Test Symposium
VDAT2010
July 7-9, 2010Chitkara University Campus, Himachal Pradesh, India
Please visit VSI publications for details on VDAT proceedings.
Search for paper details and abstracts
Softcopy proceedings: Symposium
Softcopy proceedings: Tutorials
NoC | Biomedical | Interconnect
Invited talks | Architecture | Devices | Test & Verification | Research Scholar Forum
Tutorials
Fundamentals of SoC Power Management Architecture Design and Verification
Bhanu Kapoor (Mimasic); Prapanna Tiwari (Synopsys); John Goodenough (ARM Embedded Technologies); Amit Kumar (Sirf/CSR); and Milind Padhye (Freescale)
VLSI and System Design for Solar PV Energy Management - Why, What and How
Nagavolu Murty; Mukesh Nair; Jayalakshmi P; and Mahadev Cholachagudda (NXP Semiconductors)
Network-on-Chip: The Next Generation of Multi-Processor System-on-Chip
Santanu Chattopadhyay; and Santanu Kundu (IIT Kharagpur)
Video Codecs for Embedded Multimedia Systems
Milind Phadtare (NXP Semiconductors)
An Overview of Modern-day VLSI Design and Test
C.P. Ravikumar (Texas Instruments, India)
Technical papers
Analog
CMOS Transconductance Element for Low-Frequency Applications
Venkatesh Acharya (Texas Instruments)
Design of a 10bit, 5 MS/s Pipelined ADC for CMOS Image Sensor
Kanhu Charan Behera; M. Santosh; and S.C.Bose (Central Electronics Engineering Research Institute, Pilani)
Design of 6-bit Folding & Interpolating ADC
Shruti Oza (Kalol Institute of Technology); and Niranjan Devashrayee (Nirma University of Science & Technology)
A Short Tutorial on Analog Layout Challenges in Deep Submicron Technologies
Vishwanath Hanchinal; and Vijay Mundlapudi (NXP Semiconductors India)
A Sensitivity Analysis Based Approach to Statistical Parameter Estimation of Analog Circuits
Arnab Khawas (IIT, Kharagpur); and Amitava Banerjee (National Semiconductor Corp, India)
Asynchronous ADC Using Novel Asynchronous Subranging Scheme
Anita Deshmukh; Ravi Patil; Raghvendra Deshmukh; and Rajendra Patrikar (VNIT, Nagpur)
Power Management
A Novel Curvature Compensation Technique for voltage reference circuit
K. Praveen Kumar Reddy; and Rajendra M. Patrikar (VNIT, Nagpur)
A Tutorial on Battery Simulation - Matching Power Source to Electronic System
Vishwani Agrawal; and Manish Kulkarni (Auburn University)
Low-power
Robust and Self-Adaptive Power Reduction Techniques for FIFO Buffers
Salil Gadgil; Senthilkannan C; and Anuja Bagdi (Texas Instruments India Pvt Ltd)
A Technology Specific Approach to Reduce Leakage
Sambhu Nath Pradhan (KIIT University); and Santanu Chattopadhyay (IIT Kharagpur)
Novel Low Power Multipliers using Bypassing Schemes
P Saravanan; and S Brinda (PSG College of Technology)
Design of Static Latch-based Comparators using Power Constrained Optimization
Purushothaman A; and Chetan D. Parikh (DAIICT)
Low Power Decoupling Circuit
Dharmaray Nedalgi (NXP Semiconductors)
Low Power Means to High-Speed Current Switching
K.R. Srinidhi Koushik; and Lavanya Nirikhi (Sasken Communication Tech. Ltd.)
CAD
Fast CMOS Circuit design: High Speed Library Design
Akhtar W. Alam (ARM Embedded Technologies)
Implementation of Fault Tolerant Feedforward Neural Networks in VLSI Hardware
N. Mohankumar; M. Nirmala Devi; and Jayalakshmi P. Nair (Amrita Vishwa Vidyapeetham)
Static Timing Analysis of IO Interfaces for Large SoCs
Rahul Vishal; Sagar Mallik; and Vinita Alphonsus (NXP Semiconductors India Pvt. Ltd)
NoC
Handling Multiple Hotspots in Wormhole NoCs
Hemangee Kapoor; Shirshendu Das; and B.V.Balakrishna (IIT Guwahati)
Minimal Path Fault Tolerant Routing in 2-D Mesh NoC
Navaneeth Rameshan; Manoj Gaur; Mushtaq Ahmed; and Vijay Laxmi (MNIT, Jaipur)
Biomedical
FPGA based Fuzzy Neural Signal Processing System for QRS Complex Detection in Noisy ECG Signals
Shubhajit Roy Chowdhury (Jadavpur University)
A Novel Approach to Digital Filter Implementation for Hearing Aids
Subathra Devi N; and Raja Lakshmi K (PSG College of Technology)
New Techniques for Droplet Routing in Digital Microfluidic Biochips
Pranab Roy; Tuhina Samanta; Hafizur Rahaman (BESU, Shibpur); and Parthasarathi Dasgupta (IIM, Calcutta)
Comparative Analysis of Fertilization of Human Egg Using Morphological Operations and Parameters
Interconnect
A Closed Form Expression for Slew Metric for On-chip VLSI RC Interconnects using F-distribution Function
Rajib Kar; Abirjyoti Mondal; Vikas Maheshwari; Ashis K Mal; and Anup Kumar Bhattacharjee (NIT Durgapur)
An Accurate delay Metric for Global On-chip VLSI RC Interconnects using First Three Circuit Moments
Rajib Kar; Vikas Maheshwari; M.Sunil Kumar Reddy; Vasundhara Agarwal; Ashis K Mal (NIT Durgapur); and Anup Kumar Bhattacharjee (NIT Durgapur)
Crosstalk Estimation in Coupled Interconnect lines using State Space Approach
Soorya Krishna; and M.S. Bhat (NITK, Surathkal)
Analysis of Current Mode Drivers for VLSI Interconnect Systems
Sunil Jadav; Gargi Khanna; and Ashok Kumar (NIT, Hamirpur)
Keynote and Invited Talks
Opportunity Unlimited – Emerging Markets in India
Jaswinder S. Ahuja (Corporate VP and MD, Cadence Design Systems, India)
Cloud Computing and its implication to EDA
Hasmukh Ranjan (VP Engineering Compute & Infrastructure Services, Synopsys, India)
Harnessing Power of Multi-cores
Prof.Anshul Kumar (IIT Delhi)
Design and Test of High-speed Chip-to-chip IO Interfaces to Improve TTM
Aninda K. Roy (Intel Corporation)
Architecture
Hybrid 16*16 Multiplier Based on Tree and Iterative Array concepts
Ayon Dey; Deepak Agarwal (Texas Instruments); and DV Poorniah (Bits-Pilani, Bangalore Center)
High Speed Low power Floating Point Multiplier Design based on CSD (Canonical Sign Digit)
Prabir Saha; A Banerjee; I Banerjee (Jadavpur University); and A Dandapat
Semi-auto-visual Techniques to Capture Eight Indispensible Blood Parametres at PHC
Vikal Ingle (B.D. College of Engineering, Sevagram, Wardha); and Dr Pramod B.Patil (Jaidev College of Engineering, Nagpur)
Devices
Analytical Modeling for Estimation of Drain Current in Irradiated NanoScale Double Gate FinFET Device
Surendra S. Rathod; Ashok K. Saxena; and Sudeb Dasgupta (IIT Roorkee)
Performance Evaluation of FinFET and Planar MOSFET Devices at Circuit Level for 45nm Technology
Sanjay B. Prajapati; Niranjan Devashrayee (Institute of Technology, Nirma University, Ahmedabad); Rajesh Thakker (Vishwakarma Govt. Engg. College, Chandkheda, Gujarat); Maryam Shojaei Baghini; and Mahesh B. Patil (IIT Bombay)
Fault Tolerant Design With Coupled Majority-Minority QCA Gate
Mamata Dalui (Haldia Institute of Technology); Bibhash Sen (NIT, Durgapur); and Biplab K. Sikdar (Bengal Engg and Science University)
Constant Bias Current Gain Variation Method for Weak and Strong Inversion MOSFETs
Anurag Zope; W.S. Khokle; Raghvendra Deshmukh; and Rajendra M. Patrikar (VNIT, Nagpur)
Test & Verification
PLI Based Verification Setup for Fast System Level Verification
Anin George (Sasken Communication Tech Ltd)
Reducing the Debugging Effort at FPGA Emulation
Naveen Tiwari (Samsung India Software Operations Pvt. Ltd)
Signature Based Successive Reduction Diagnosis Flow for Embedded Read-Only Memories in a BIST Environment
Suraj Prakash (ST Microelectronics)
Research Scholar Forum
CMOS-LTE Comparator and 2:1 Multiplexer in Flash ADC Design
Meghana Kulkarni (GIT, Belgaum, Karnataka, India); V. Sridhar (P.E.S. College of Engineering, Mandya); and G. Kulkarni (Gogte Institute of Technology, Belgaum, Karnataka)
A FinFET based Robust Sense Amplifier for Process Variations
Vivek Harshey; Ashok K. Saxena; and Sanjeev Manhas (IIT Roorkee)
Design of a Novel CNTFET-Based 1-Bit Full Adder in Deep Submicron Technology
Aminul Islam (BIT, Mesra, Ranchi); Sachin Pable; M.W. Akram; and Mohd. Hasan (AMU, Aligarh)
Design of Robust Subthreshold Circuits
S.D. Pable (AMU, Aligarh); Aminul Islam (BIT, Mesra, Ranchi); M.W. Akram; and Mohd. Hasan (AMU, Aligarh)