13^th IEEE/VSI VLSI Design And Test Symposium
VDAT2009

---

Download abstracts (PDF 3795 kb)

Analog VLSI Design | Design Automation | Digital VLSI Design | FPGA | Low-power
Low Power Design and Test | Verification | VLSI in Biomedical | VLSI in Communication
VLSI in Test | Invited talks | Research Scholar Forum

Analog VLSI Design

CMOS Analog ASIC Design of Inverse Delayed Function Model of a Neuron for ANN
Niteen Futane, Shubhajit Roy Chowdhury (Jadavpur University), Chirasree Roychoudhuri (Bengal Engineering and Science University, Shibpur), and Hiranmay Saha (Jadavpur University)

Session 2A-3 Analog VLSI Design-1 Regular Paper

Clock-free Leakage-feedback Gate MTCMOS Flip-flop with a Centralized Sleep switch
Rahul Singh (IT-BHU, Varanasi)

Session 2A-3 Analog VLSI Design-1 Regular Paper

A 1.8mW, 320MHz Sigma Delta ADC for Wireless Applications
Harish Chandrababu (IISc Bangalore), and Jamadagni H.S. (CEDT, IISc Bangalore)

Session 2A-3 Analog VLSI Design-1 Regular Paper

A High Performance Reference Circuit using Low Input Offset Operational Amplifier
Anil Saini, and Kapil Kumar Rajput (CEERI)

Session 2A-7 Analog VLSI Design-2 Short Paper

Impact of Process Variability on 28nm Analog CMOS Performance
Ajayan K.R, and Navakant Bhat (IISc, Bangalore)

Session 2A-7 Analog VLSI Design-2 Short Paper

A 1.2-V 5.3–7.3GHz Wideband Quadrature LC Voltage Controlled Oscillator
Mohit Garg, M Sultan M Siddiqui, and B Bhaumik (IIT Delhi)

Session 2A-7 Analog VLSI Design-2 Short Paper

Design Automation

Surface Potential Based Current Modeling of Thin Silicon Channel Double and Tri-Gate SOI FinFETs
Robin Prakash, Rohit Yadav (BITS, Pilani), and Subhash Bose (Central Electronics Engineering Research Institute, Pilani)

Session 3C-5 Design Automation Short Paper

Uniform Thermal Distributions in Placement of Standard Cells and Gate Arrays: Algorithms and Results
Prasun Ghosal, Hafizur Rahaman (Bengal Engineering & Science University), and Partha Dasgupta (IIM Calcutta)

Session 3C-5 Design Automation Short Paper

Simulation of Improved Dynamic Response in Active Power Factor Correction Converters
Matada Mahesh, and Anup Kumar Panda (NIT Rourkela)

Session 3C-5 Design Automation Short Paper

Digital VLSI Design

An Alternate Approach to Enhance Parallel Decimal Multiplier Performance
Rekha James, K. Poulose Jacob (CUSAT, Cochi, Kerala), and Sreela Sasi (Gannon University)

Session 2B-7 Digital VLSI Design Regular Paper

Hardware Implementation of Dlighting Module for using it in a Digital Camera Chip
Gaurav Agarwal, Amit Singhal, Anu Gupta, and Prayush Kumar (BITS Pilani)

Session 2B-7 Digital VLSI Design Short Paper

An Algorithm for High speed, Low power Implementation of Modular Multiplier
Raju Lampande, Chandrashekhar Kukade, Raghvendra D Deshmukh, and Rajendra Patrikar (Visveswaraya National Institute Of Technology, Nagpur)

Session 2B-7 Digital VLSI Design Short Paper

FPGA

Design of Run Time FPGA Router using JBits 3.0
Hafizur Rahaman (Bengal Engg. & Sc. Univeristy), Nachiketa Das (Marine Engineering and Research Institute, Kolkata), Pranab Roy (BESUS, Shibpur)

Session 3C-4 FPGA Short Paper

A High Performance Implementation of LU Decomposition on FPGA
Manish Kumar Jaiswal, and Nitin Chandrachoodan (IIT Madras, Chennai)

Session 3C-4 FPGA Short Paper

Constructing Synthetic Benchmark Circuits to Stress Test FPGAs
L Srivani, Veezhinathan Kamakoti (IIT Madras), and Ilango Sambasivam (IGCAR, Kalpakkam)

Session 3C-4 FPGA Short Paper

Low-power

A Novel Low Power and High Read Stability SRAM Cell
Sivamangai N.M, Saravanan P, and Gunavathi K (PSG College of Technology)

Session 2C-3 Low Power Regular Paper

Peak Dynamic Power Estimation of FPGA-mapped Digital Designs
K Shyamala, Shoaib Mahammad, and Veezhinathan Kamakoti (IIT Madras)

Session 2C-3 Low Power Regular Paper

Low-Power Adiabatic Flip-flops and Sequential Circuits using ACPL
Sreenu D, Ashok Saxena, and Sudeb Dasgupta (IIT Roorkee)

Session 2C-3 Low Power Regular Paper

Low Power Design and Test

A Centralized BIST Infrastructure Design for Stuck-At Fault Detection In SoC
Rupsa Chakraborty, and Dipanwita Roy Chowdhury (IIT Kharagpur)

Session 3B-4 Low Power Design and Test Short Paper

Low Power Test Implementation through Temporal Spreading of Scan Shift/Capture and Q-Gating
Pranay Kotasthane, Sireesha Arisetti, Sreeram Chandrashekar, Kishore Kumar Robbi, Vishal Usapkar and Anirban Saha (Texas Instruments India)

Session 3B-4 Low Power Design and Test Regular Paper

Capture Power Reduction for Modular System-on-Chip Test
Jaynarayan Tudu (IISc, Bangalore), Erik Larsson (Linkoping University), Virendra Singh (IISc, Bangalore), and Adit Singh (Auburn University)

Session 3B-4 Low Power Design and Test Regular Paper

Verification

Virtual Platform for System Integration and Functional Test
Praveen Kumar (NXP Semiconductors India Pvt Ltd)

Session 2A-5 Verification Short Tutorial

VMM Methodology Template Code Generator
Lakshman Easwaran, Vasantha Kumar, Siva Shankar Kuppam, and Ranjith OJ (MindTree Ltd)

Session 3A-2 Verification Short Tutorial

Addressing Via Density in UDSM Technologies using a Flexible Correct-by-Construction Approach
Dibyendu Goswami, Swami Gangadharan, and Albert Holguin (Intel)

Session 2A-5 Verification Regular Paper

Relevance of Gate Level Simulations in Today's SoC Verification
Vishal Dalal (SASKEN Communication Technologies Limited)

Session 2A-5 Verification Short Tutorial

Reduced Verification Effort for Low power SoC by using Right Integration, Simulation and QC Strategy
Mayank Jindal, Gokulakrishnan Manoharan, Sarveswara Tammali, and Ayon Dey (Texas Instruments India)

Session 2A-5 Verification Regular Paper

A Strategy and Framework for Processor Verification
Asheesh Shah (King Saud University, Saudi Arabia), Ashwani Ramani (Devi Ahilya Vishwavidhyalaya, Indore), AbdulAziz Mazyad, and Hamid Elsemary (King Saud University, Saudi Arabia)

Session 3A-2 Verification Short Tutorial

VLSI in Biomedical

FPGA based Fuzzy Processing System for Advance Detection of Obstructive and Restrictive Pulmonary Disorders
Shubhajit Roy Chowdhury, and Hiranmay Saha (Jadavpur University)

Session 2C-5 VLSI in Biomedical-1 Regular Paper

An Embedded Solution of 2-D Fast Affine Transform for Biomedical Imaging Systems
Pradyut Biswal, and Swapna Banerjee (IIT Kharagpur)

Session 2C-5 VLSI in Biomedical-1 Regular Paper

Ultra Low Power Digital to Analog Converter
Raj Dua, Sumeet Tiwana, and Anu Gupta (BITS Pilani)

Session 2C-5 VLSI in Biomedical-1 Short Paper

Process, Temperature, Voltage (PTV) & Load Compensation for IOs
Vikas Narang (Texas Instruments), Nitin Chandrachoodan (IIT Madras, Chennai), Vinod Menezes (Texas Instruments)

Session 2C-5 VLSI in Biomedical-1 Regular Paper

Switch Error and Total Harmonic Distortion Improvement Technique in SHA
Rohit Yadav (BITS, Pilani)

Session 2C-7 VLSI in Biomedical-2 Short Paper

Analysis of Single Event Upset for Biomedical Applications
Surendra Rathod, Ashok Saxena, and Sudeb Dasgupta (IIT Roorkee)

Session 2C-7 VLSI in Biomedical-2 Short Paper

Weak Inversion based Low Power Low Noise Sixth order gm-C Filter at 1V for ECG Application with 180nm Technology
Anurag Zope, Waman Khokle, Raghvendra D. Deshmukh, and Rajendra Patrikar (VNIT Nagpur)

Session 2C-7 VLSI in Biomedical-2 Short Paper

EEG-based Driving Fatigue Estimation using Discrete Wavelet Transform
Sangeeta Panigrahy (KITS, Warangal)

Session 2C-7 VLSI in Biomedical-2 Short Paper

VLSI in Communication

High Speed Leading One Bit Detection based New Scaling Free CORDIC Algorithm
Supriya Aggarwal, Kavita Khare, and Nilay Khare (MANIT)

Session 2B-3 VLSI in Communication-1 Regular Paper

VLSI Implementation of Motion Vector Recovery Algorithms for H.264 based Video Codecs
Kavish Seth, Muralidhar Komisetty, Vamshi Anand, Veezhinathan Kamakoti, and S Srinivasan (IIT Madras)

Session 2B-3 VLSI in Communication-1 Regular Paper

Mixed-Clock Interconnect FIFO Design
Rakesh Yarlagadda, Jalapally Karthik, and Hemangee Kapoor (IIT Guwahati)

Session 2B-3 VLSI in Communication-1 Regular Paper

Design and Analysis of Low Power Viterbi Decoder for CDMA System
Ketki Joshi, Anand Darji, and Upena Dalal (SVNIT, Surat)

Session 2B-5 VLSI in Communication-2 Short Paper

Design of Multiple Output, Field Programmable CMOS Voltage Reference using Floating Gate Transistors
Arsh Josan, Karan Kumar, and Chota Markan (Dayalbagh Educational Institute, Agra, UP)

Session 2B-5 VLSI in Communication-2 Regular Paper

Performance Evaluation of an Efficient Boolean Function Generator for Cryptographic Applications
Debdeep Mukhopadhyay (IIT Kharagpur), and Ankur Sharma (IIT Madras)

Session 2B-5 VLSI in Communication-2 Regular Paper

VLSI Test

A Novel Test Method for Fault Detection in RF Circuits
Saravanan P, Brinda Subburaj, and Kalpana Shekar (PSG College of Technology)

Session 3C-2 VLSI Test-1 Regular Paper

Prime Numbers are High Coverage Test Vectors!
Vasanthkumar Ramesh, Akanksha Jain, Veezhinathan Kamakoti (IIT Madras), and Vivekananda Vedula (Intel Technology Pvt. Ltd)

Session 3C-2 VLSI Test-1 Regular Paper

Bounds on Defect Level and Fault Coverage in Linear Analog Circuit Testing
Suraj Sindia, Virendra Singh (IISc, Bangalore), and Vishwani Agrawal (Auburn University, Alabama, USA)

Session 3C-2 VLSI Test-1 Regular Paper

Performance Evaluation of Mesh-of-Tree Based Network-on-Chip Using Wormhole Router with Poisson Distributed Traffic
Santanu Kundu (IIT Kharagpur), Radha Purnima Dasari (Texas Instruments, Bangalore), Kanchan Manna, and Santanu Chattopadhyay (IIT Kharagpur)

Session 3B-5 VLSI Test-2 Short Paper

Synthesis of Analog Inputs for Testing of Digital Modules in Mixed Signal VLSI Circuits
Chiranjeevi Yarra (IIT, Kharagpur), Santosh Biswas (IIT, Guwahati), and Siddarth Mukhopadhyay (IIT, Kharagpur)

Session 3B-5 VLSI Test-2 Short Paper

BIST / Test-Decompressor Design using Combinational Test Spectrum
Nitin Yogi, and Vishwani Agrawal (Auburn University)

Session 3B-5 VLSI Test-2 Regular Paper

Keynote and Invited Talks

From emerging to emerged economy: Need for a Technology Infrastructure in India
Dr. Biswadip (Bobby) Mitra (President and MD, Texas Instruments India)

Session 2A-1 Keynote Talk-1 Keynote talk

Embedded Systems: Growing complexity and augmented role of software
V.R.Venkatesh (Sr. Vice President - Product Engineering Services, Wipro Technologies)

Session 2A-4 Keynote Talk-2 Keynote talk

Need for Energy Efficiency and Smart grids: Role of Semiconductors in future
Dr.Sunit Tyagi (CEO, InSolare Energy Private Limited)

Session 3A-1 Keynote Talk-3 Keynote talk

How to Accommodate Design Changes using Standard Cell Library PDF 266 KB
Radhika V. Guttal, Harish Venkatesh, and Akhtar W. Alam (ARM Embedded Technologies)

Session 3A-4 Invited talks Presentation

Research Scholar Forum

TIQ Technique based Optimized Analog to Digital Converter
Meghana Kulkarni (G.I.T. Belgaum), Dr. V. Sridhar (P.E.S. College of Engineering, Mandya), and Dr. Gururaj Kulkarni (KLS Gogte Institute of Technology, Belgaum)

Session 3A-4 Research Scholar Forum RSF

FPGA Implementation of Visible Watermarking Processor
Hitendra Gupta (LNMIIT), and Kamlesh Sharma (MNIT)

Session 3A-4 Research Scholar Forum RSF

Performance Analysis of Low power 6T SRAM Cell in 180nm and 90nm
Sreeramareddy G.M. (S V College of Engg & Tech), and Ch. Chandrasekarareddy P (JNTUCE, Hyderabad)

Session 3A-4 Research Scholar Forum RSF

 

Analog VLSI Design | Design Automation | Digital VLSI Design | FPGA | Low-power
Low Power Design and Test | Verification | VLSI in Biomedical | VLSI in Communication
VLSI in Test | Invited talks | Research Scholar Forum