9^th VLSI Design And Test Symposium
VDAT2005

… Analog Design …

S. Moghe, Santhosh Biswas, J.K. Agrawal, D. Sarkar, S. Mukhopadhyay and A. Patra, IIT Kharagpur
A Hybrid System Approach to Failure Diagnosis of Analog VLSI Circuits: A Case Study of DC-DC Buck Converters

Uday Goel, Sachit Grover and G.S. Visweswaran, IIT Delhi
Low Voltage Current Mode Pipelined Analog to Digital Converter

K.S.R. Krishna Prasad, N. Suresh and B. Swapna, NIT Warangal
A 1.2V Low Power CMOS Bulk Driven Operational Amplifier

… Applications …

Debdeep Mukhopadhyay and Dipanwita Roy Chowdhury, IIT Kharagpur
Programmable Galois Multiplier Using Cellular Automaton

Gaurav Singh Nim, B.S. Chauhan and Asheesh Thapliyal, IRDE, Dehradun
Real-Time Image Processing System

Harsh Dhand, Neeraj Goel, Mukesh Agarwal and Kolin Paul, IIT Delhi
Partial and Dynamic Reconfiguration in Xilinx FPGAs – A Quantitative Study

Poster Papers: Applications

Jagadesh Palaniswamy, G. Elangovan and P. Vanaja Ranjan, College of Engineering, Anna University
SoC Implementation for Hearing Aid Noise Recognizer

Kotte D.N.V.S. Prasad, Rajeeva G.K. and Manoj Jain, Central Research Laboratory, BEL
A Generic Time Division Duplex Scheme for Synchronous Traffic and Control of Remote Communication Devices

Shubhajit Roy Chowdhury and Hiranmay Saha, Jadavpur University, Kolkata
VHDL Model of a Cognitive System for Telemedicine Applications

Samir Roy, National Institute of Technical Teachers’ Training & Research, West Bengal
A Universal Logic for Quantum-Dot Cellular Automata

Sahil M. Bansal, Punjab Engineering College and Dipankar Nagchaudhuri, DA-IICT
Minimization in Variation of Output Characteristics of a SOI MOS Due to Self-Heating

M. Ayoub Khan and Y.P. Singh, CDAC, Noida
Omura’s Modular Addition for FPGA Implementation of IDEA Cipher Block

Naveen H.N. and N. Shekar V. Shet, NITK, Surathkal
Performance optimized VLSI Implementation of RC5 Encryption Algorithm

S. Anandh, L. Karthick, Ponnambalam Lakshmanan, S. Rajaram and V. Abhaikumar, Thiagarajar college of Engineering, Maduarai
FPGA Implementation of OFDM WLAN Modem

… Architecture …

Preeti Ranjan Panda, IIT Delhi and Viresh Kumar, Infineon Tech., Bangalore
A technique for predicting the effect of Data Cache Associativity

Chandan Karfa, J.S. Reddy, S. Biswas, C.R. Mandal and D. Sarkar, IIT Kharagpur
SAST: An Interconnection Aware High-level Synthesis Tool

Sanjukta Bhanja and Thara Rejimon, University of South Florida, USA
Probabilistic Error Model for Unreliable Nano-logic Gates

… Circuits and Devices …

Poster Papers: Circuits and Devices

H. Mangalam, S. Subramanian, Sri Krishna College of Engg. & Tech, Coimbatore and K. Gunavathi, G. Prabhu, PSG College of Technology, Coimbatore
Domino Logic with Variable Body Biased Keeper

Vijayakumar Ponnusamy, M. Shanthanalakshmi and K. Gunavathi, PSG College of Technology, Coimbatore
Efficient Energy Recovery Technique for Positive Feedback Adiabatic Logic

A. Annada Prasad, Deepanjan Datta, Samiran Ganguly and Sudeb Dasgupta, Indian School of Mines, Dhanbad
Extraction of Gate Tunneling Current in Gaussian Doped High-k Ultra-Thin-Body Double Gate (DG) MOSFET

Lalitha Mohana Kalyani Garimella, Annajirao Garimella, Laura Escobedo and Jaime Ramirez-Angulo, New Mexico State University, USA
Compact Low Voltage VHF Continuous –Time Current Mode Filters Based on First Order Low-Pass Building Blocks

… Design Techniques …

Kiran Kumar Muralidharan, Wipro Technologies
Mixed design of Self-Timed Logic in Synchronous Systems (Embedded Tutorial)

Akhilesh Chaudhary, Gaurav Gupta and M. Balakrishnan, IIT Delhi
Factoring Large Numbers using FPGA

M.S. Bhat, Rekha S. and H. S. Jamadagni, CEDT, IISc Bangalore
Multi-level Current-mode Signaling for Long High-Speed Interconnects

Venkatesh B.S. Acharya, Sandip Kakde, Tantry Shashidhar and Koyama Hiroshi, Sanyo LSI Technology
Design and Implementation of Class AB CMOS Power Amplifier using GSMC 0.15u Technology

… DSP …

N.J.R. Muniraj, Sona College of Technology and R.S.D. Wahida Banu, Government College of Engg, Salem
On ways to improve the Adaptive Filter Technique using Verilog HDL and CPLD

G. Seetharaman, B. Venkataramani and G. Lakshminarayanan, NIT, Tiruchirappalli
Design and FPGA Implementation of Wavepipelined Image Block Encoders using 2D-DWT

Satyendra Kumar, K.S Ramesh, Anbuselvi J. and Subham Roy Choudhury, Central Research Laboratory, BEL
FPGA Implementation Of Soft Decision Viterbi Decoder

… EDA …

Hafizur Rahaman, Bengal Engg. & Science University, Debesh K. Das, Jadavpur University and Bhargab B. Bhattacharya, IIT Kharagpur
Synthesis and Testing of Reversible Logic – A Survey (Embedded Tutorial)

Subhashis Mandal, Soumya Pandit, Abhishek Somani, Shamik Sural and Amit Patra, IIT Kharagpur
UML based Object Oriented Methodology for Analog Test Structure Design Automation

Bodhisatya Sarker, Cadence Design Systems
Petri Net Modeling of GALS and Implementation in Baseband Datapath component of an IEEE 802.11a compliant modem

Arnab Sarkar, P.P. Chakrabarti and Rajeev Kumar, IIT Khargpur
Boundary Fair Round-Robin: A Fast Fair Scheduler

Sanjay Chatterjee, IIT Khargpur, P.P. Chakrabarti and Rajeev Kumar
An Optimal Algorithm for Register Renaming: A Post Compilation Technique

Poster Papers: EDA

Aruleaswari G. and V. Lakshmi Prabha, Government College of Technology, Coimbatore
An Adaptive Algorithm for power management at system level

Subhashis Mandal, Abhishek Somani, Jitendra Agarwal, Shamik Sural and Amit Patra, IIT Kharagpur
Crosstalk aware Line Search Algorithm for Analog Routing

J.V.R. Ravindra, K.S. Sainarayanan and M.B. Srinivas, International Institute of Information Technology, Hyderabad
A Novel Bus Coding Technique for Low Power Data Transmission

Santanu Chattopadhyay, IIT Kharagpur, Himanshu Agarwal and Mohit Chawla, IIT Guwahati
Evolving Cellular Automata for Low power Testing of Circuits

… Low Power …

Soujanna Sarkar and Subash Chandar G., Texas Instruments India
Low Power Techniques for CMOS Designs (Embedded Tutorial)

Siri Uppalapati, GDA Technologies, Inc., USA, Michael L. Bushnell, Rutgers University and Vishwani D. Agrawal, Auburn University
Glitch-Free Design of Low Power ASICs using Customized Resistive Feedthrough Cells

Alex P. James and Ajayan K.R., College of Engineering, Trivandrum
Nanoscale design of Low power Supply Pseudo Resistive Cascode Current Mirror

Rajarshi Paul, Amit Patra and Sidhartha Mukhopadhay, IIT Kharagpur

Verilog - A Modeling of Parasitic and Biasing effects in PSRR behavior of Brokaw Bandgap Voltage Reference

V. Lakshmi Prabha, K. Balamurugan, GCT, Coimbatore and Elwin Chandra Monie, Government college of Engineering, Vellore
Online Adaptive Power Management for Non-Stationary Service Request

… Memory Design …

Ashish Sampatraj Kothari, Purplevision Technologies
Area Optimization Tips in Memory BIST

Anandshankar S. Mudlapur, Vishwani Agrawal and Adit Singh, Auburn University, USA
A Novel Random Access Scan Flip-Flop Design

Vasudha Gupta and Rengarajan Krishnan, Texas Instruments India
An Accurate Critical Path Based Characterization Scheme for Memory Compilers

… Synthesis …

Sourav Saha, S. Sarkar, V.K. Tandon, IIT Roorkee and Susmita Sur-Kolay, Indian Statistical Institute
Comparative Study of Logic Synthesis Objectives in FPGA Design Flow

M.S. Bhat, Rekha S. and H.S. Jamadagni, CEDT, IISc, Bangalore
Synthesis of Multiple-Valued Arithmetic Functions using Evolutionary Process

Aneesh Bhasin, Sameer Arora and Mukesh Ameria, HCL Technologies, Noida
Enabling ESL Design Through Behavioral Synthesis

… Testing …

Thakur Sanjay Kumar, A. N. Chandorkar, IIT Bombay and Rubin A. Parekhji, Texas Instruments India
Diagnostic Testing of Memories for Static and Dynamic Faults

Prasenjit Basu, Sayantan Das, Ansuman Banerjee, Pallab Dasgupta and Partha Pratim Chakrabarti, IIT Khargpur
Test Plan Coverage by Formal Property Verification

Shibaji Banerjee and Dipanwita Roy Chowdhury, IIT Kharagpur
An Integrated Computer Aided Test (CAT) Tool for System on Chip

Sarveswara Tammali, Jais Abraham, TI India, Thuan Hoang, Texas Instruments Inc. and Russ Kneupper, Stafford, Texas, USA
Testing methods, Parameters and Test sequencing for VLSI Devices (Embedded Tutorial)

Sanjeev Kumar Sharma, Wipro Technologies
Effect of Timing Jitter on High Speed Data Converter System

Alok S. Doshi and Vishwani D. Agrawal, Auburn University, USA
Independence Fault Collapsing

T. Chandra Sekhara Reddy, M. Veera Raghavulu, P. Kalpana, P.T. Vanathi and K. Gunavathi, PSG College of Technology, Coimbatore
On-Line BIST for Testing of Operational Amplifiers

Poster Papers: Testing

Sathis Kumaran Nathappan, M. Veera Raghavulu and P.T. Vanathi, PSG College of Technology, Coimbatore
CMOS SRAM Fault Detection Using Dynamic Power Supply Current

D. Mukhopadhyay and Niladri Narayan Mojumder, Jadavpur University
Energy-Performance Improvement of Content Addressable Memory by Dual-Threshold CMOS Technology

Seema Bawa, Thapar Institute of Engineeing & Technology, Patiala and G.K.Sharma, IT Group, IITM, Gwalior
Search Space Pruning for Faster Test Generation based on Parallel and Adaptive GA

… Verification …

Suchismita Roy, Pallab Dasgupta and P.P. Chakrabarti, IIT Kharagpur
Bounded Model Checking for Open LTL

Sayantan Das, Prasenjit Basu, Pallab Dasgupta and Partha Pratim Chakrabarti, IIT Kharagpur
Syntax-driven Approximate Coverage Analysis for an Assertion Suite against a High-level Fault Model

Kaushal Jha, Arindam Raychaudhuri, Dinesh Jain, Shubha Govindachar, David Phelan, Analog Devices and Prem Swaroop, North Carolina State University, USA
A 16-bit, 200uA, 10us, Monotonic DAC Converter in SOT-23 package

Santanu Chattopadhyay, IIT Kharagpur, Goutam Das and H. Bhoumik, SIT Siliguri
Integrated Core and Interconnect Testing with Test-time and Scan Power Minimization