Design

Keynote

Ralf Pferdmenges
Design Methodology for sub-0.1 um Technologies

Dinesh Sharma, IIT Bombay
VLSI Education in India: Obvious Questions, Difficult Answers
Download foils PDF, 277 KB

Sunil Sherlekar, TCS
The Silicon Saga: Recapitulating the Past & Speculating the Future
Download foils PDF, 114 KB

Analog

M. Shankaranarayana Bhat, Rekha S. and Jamadagni H S.
Design of Current-mode CMOS Multiple- valued Latch

G.Suresh, G.L.Biswas, K.D.N.V.S.Prasad and A.T.Kalghatgi.
Configurable I/Q Modulator using Cordic based DDS Architecture

M. Shankaranarayana Bhat and Jamadagni H S.
Design of Current-mode Flash ADC

Memory

Sreedhar Natarajan
Emerging Non Volatile Memory: Technological Promise Or Industrial Hoax

Embedded

Atanendu Sekhar Mandal, Ravi Saini, Pramod Tanvar, Nitin Sharma, S.C.Bose, Raj Singh and Chandra Shekhar
Designing an Embedded Processor: Specifications to Implementations

Logic

P Vijayakumar and K Gunavathi
Performance Optimization Of CMOS Circuits Using Retiming Algorithm With Stepwise Charging

S. Sarkar, Rajeevan Chandel and R.P. Agarwal
Voltage-Scaled Repeaters for Low- Power Long Interconnections in VLSI Circuits

Subhendu Kumar Sahoo, Chandra Shekhar and Anu Gupta
A Compact Fast Parallel Multiplier Using Modified Equivalent Binary Conversion Algorithm

Sridhar Krishnamurthy and T.R.Sivaramakrishnan
Implementation of Advanced Encryption Standard (AES) algorithm in a resource limited FPGA

Hande V, Uday Prabhu and Shardul Bapat
Real Time Interface between Automotive ECUs and a Simulator

Chandra Mohan Umapathy
High Speed Squarers

T.S.B.Sudarshan and Ganesh T.S.
Hardware Architecture for Message Padding in Cryptographic Hash Primitives

Ganesan S Iyer and Rajendra M. Patrikar
An Application of Neural Network Learning to Physical Design Optimization in VDSM Technology

Dipankar Das, Rajeev Kumar and Partha P. Chakrabarti
Code Compression using Unused Encoding Space for Variable Length Instruction Encodings

V. Appandai Raj, D. Jovin Vasanth Kumar, R. Madhu Karthikeyan, S. Rajaram and V. Abhai Kumar
FPGA Implementation of OFDM Transceiver

Prashant Ramrao Deshmukh and A.A. Ghatol
FPGA Implementation of DWT Based Image Compression Coder

FPGA

Shaila Subbaraman and Vaishali V. Patil
FPGA/CPLD Based Solution to Stretch the Speed of Microprocessor / Microcontroller Based Instrumentation

B. Venkataramani, G. Lakshminarayanan, M. Yousuff Shariff, T. Rajavelu and M. Ramesh
Self tuning circuit for FPGA based wave pipelined multipliers

Gaurav Singh Nim and B.S.Chauhan
FPGA Implementation of Multiple Target Segregator

DSP

G Thavasi Raja, S. Rajaram and V. Abhai Kumar
An FPGA Implementation of Code Phase Shift Keying Baseband Decoder

Prashant Ramrao Deshmukh and A.A. Ghatol
FPGA Implementation of Subband Image Encoder using Discrete Wavelet Transform

Arun Chokkalingam, V.Thiyagarajan, S.Sasikumar and M.Madheswaran
Implementation of Convolutional Encoder and Hard-decision Viterbi Decoder in FPGA

Soujanna Sarkar and Subash Chandar Govindarajan
Embedded Tutorial : DSP Architectures

Anidya, Vaishali B Mungurwadi and A.S.Dhar
VLSI Implementation of Viterbi Decoder

Mallikarjunaswamy S. Muttad, Ashok Rao and D.V. Poornaiah
Systolic Array based VLSI Architecture for Motion Estimation in Video Compression Applications

Physical Design and Technology

EDA

Nidhi Sawhney, Shabbir Batterywala, Narendra Shenoy and Richard Rudell
Parallelizing a Statistical Capacitance Extractor

Subhashis Mandal, Abhishek Somani, Shamik Sural, Robert Drury and Amit Patra
A Connection Graph based Variable Wire Width Approach to Analog Routing

Sreekanth K M, Lionel Dahyot and Vinod Kumar
Novel Approach to Solve IP Integration Problems in an Era of SOC

Crosstalk

Ravishankar Arunachalam and Aniket Singh
Maximization of Aggressor Influence in Crosstalk-Delay Testing

Sachin Shrivastava and Sreeram Chandrashekhar
Crosstalk Noise Analysis at Multiple Frequencies

Sushrant Monga, Paras Garg and Frederic Hasbani
A Mathematical Analysis of Analog and Digital summation techniques in compensation Block for I/O Buffers

Circuits

Anil V Nandi, Saumen Das and S.K.Lahiri
Development of Silicon Piezoresistive Accelerometer for Avionics Applications+

Sunil Kumar Vashishtha and Basabi Bhaumik
1.5V, 10-bit, ±1200 mV Input range, CMOS, Pipelined Analog-to-Digital Converter

Venkatesh C. and Navakanta Bhat
A MEMS Oscillator based on displacement sensing principle

Technology

Anuj Madan, Sumeet Jindal, B.Prasad and P.J.George
An Efficient Monte Carlo Device Simulator to calculate Velocity Ovesrhoot in MOSFETs

Harish B.P., Srinivasan R., and Navakanta Bhat
Process Sensitivity Evaluation of 90nm CMOS Tecnology With Gate-to-Source/Drain Overlap Length as a Device Design Parameter

Suresh Nalluri and A.P.Shiva Prasad
Response Surface Methodology Based Design Approach for Yield Enhancement of Analog Integrated Circuits

Kanishka Biswas, S. Das, K. Dey, D. K. Maurya and S. Kal
Study of Single Crystalline Silicon (100) Surface Topography Etched in KOH Solution

Sudeb Dasgupta and Ritambhar Roy
Charactersiation of Gate Oxide Leakage Current of NANO-MOSFET Using Green's Function Approach

Rajesh Kumar Sangati, Sowjanya Syamala and Navakanta Bhat
Capacitance Sensing Techniques for MEMS Gyroscope

Srinivasan R and Navakanta Bhat
Reassessment of Channel Engineering in Sub-100nm MOSFETs

Ganesan.S.Iyer and Rajendra.M.Patrikar
Effect on Surface Roughness on Physical Design Parameters

Power

Syed Saif Abrar
Early, Fast & Accurate Software Power Estimation for Embedded Digital Signal Processors

Lakshmi Prabha Viswanathan and Elwin Chandra Monie
Power Estimation in Embedded Systems from a Pre-characterized Module Library

Lakshmi Prabha Viswanathan and Elwin Chandra Monie
Dynamic Power Management in an Embedded System for Multiple Service Requests

Siddharth Tata, Siddharth Garg and Ravishankar Arunachalam
Gate Level Dynamic Power Estimation in the Presence of Varying Process Parameters

Satya Sridhar Narayanabhatla, Kiran Satyamangala Jaisimha and Binoj Xavier
nWATT: Power Planning Methodology In Physical Design

Poster Papers - Physical Design

J.Manikandan, M.Jayaraman and M. Jayachandran
Electronic Flow Regulator (EFR) using Field Programmable Gate Arrays (FPGA)

H.Mangalam, K.Gunavathi and S.Subramanian
A Low Power Asynchronous Pipeline FIFO

Poorva Waingankar and Archana Kale
Generation of Critical Sub-graphs for Timing Analysis of Digital Circuits using Logical Pruning

G. Seetharaman, B. Venkataramani and G. Lakshminarayanan
Design and FPGA implementation of wavepipelined distributed arithmetic based filters

T.Kalaivani and S.Arumugam
Design and Implementation of ECG Codec in FPGA

P.Kalpana and K.Gunavathi
An Approach to the Classification of Analog and Mixed Signal Circuits in an Oscillation based Testing Scheme using Wavelets

Mrinal Sharadchandra Puranik and D.C.Gharpure
FPGA Based Multilayer Feedforward Neural Network and its Applications for Odor Sensing

Josemin Bala G, Poonkuzhali N and Raja Paul Perinbam J
Energy Recovery Low Power CAM Design

Pratap Ghorpade, Marthand Patil and Yamini Sharma
Design of Syndrome Calculation for Reed Solomon Codes

Subhankar Das, Raviraj Vader and Mahesh Kamat
On-Rail-Passenger Information System (ORPIS)

Namita Mujumdar and Akshata Mahale
VLSI Implementation of I2C Interface (Slave part)

K. De and S. Kal
A CMOS Analog Front-end for MEMS Sensor Interface Circuit

Y.V.Ramana Rao, N.Venkateswaran and S. Sundar
High Speed Circuit Design for 4-bit and 8-bit Unsigned Integer Squarer

S.Ramanarayana Reddy and Parimala N.
Processor Selection for Embedded System Design by using SGA

N.J.R.Muniraj, R.S.D.Wahida Banu and M.Ramya
VLSI Implementation of Canceling Maternal ECG from Fetal ECG

Anand Yaligar, Aditya Desai and Vinayak Bhat
CMOS Implementation of Cellphone Interface

Test and Verification

Test

Sarath Kumar Reddy, Ravi Dasari and Venkata Rangam
An ATPG Approach for 2-D Array Configurable Logic Structures

Shantanu Gupta, Santanu Chattopadhyay and Tarang Vaish
A Novel Approach to Reduce Test Power Consumption

Susanta Chakraborti, Pradyut Sarkar and Arindam Karmakar
Fault Diagnosis by Spectral Method

Debesh Kumar Das and Bhargab Bhattacharya
Redundancy and Undetectability of Faults in Logic Circuits: A Tutorial

Vishal Dalal
Single Full Chip Vector for Functional Testing

Sarveswara Tammalli and Jais Abraham
Hierarchichal ATPG Static Pattern Compression

Validation

N.Vijayaraghavan and Dimple Lalwani
Automated Silicon Debugging Methodology for Validating Standard Cells

Subhashis Mandal, Siddhartha Mukhopadhyay, Amit Patra and Santosh Biswas
A BIST Approach to On-Line Monitoring of Digital VLSI Circuits: Theory, Design and Implementation

Subash Chandra Bose, CEERI, Vishal Gupta and Dinesh Jain
Fault Observability Analysis of CMOS Op-amp in Frequency domain

Verification

Sunil Kakkar
Advanced Processor Architectures- The Verification Challenge

Pritam Roy, Pallab Dasgupta and P P Chakrabarti
An Assertion-based Language for Generating Test Sequences for Complex Temporal Behavior

K. Uday Bhaskar, G. Chandramouli, and V. Kamakoti
Parikhsa - A functional Verification Architecture for x86 Processors

Bhaskar Pal, A. Banerjee, P. Dasgupta, P.P. Chakrabarti and K. Chaitanya
A Simulation Coverage Metric for Analyzing the Behavioral Coverage of an Assertion Based Verification IP

Poster Papers

J.Ramesh, D.DineshKumar, M.Veeraragavalu and K.Gunavathi
A Novel CMOS BIST scheme for On-Chip ADC and DAC testing

P.Kalpana, L.Gautham, S.Mahesh and K.Gunavathi
A Novel Test Method for Analog Circuits using Wavelet Analysis

P.Nandi, T.Pattnayak, S.Biswas, S.Mukhopadhyay and A.Patra
A New Approach to Analog Scan using Time Delays

Education

Shekhar Pradhan and Felica W. Blanks, Bluefield State College, West Virginia, USA
The Role of Institutional Development and Advancement Office in Promoting Undergraduate VLSI Education - A Role Model Concept

Vineet Sahula, MNIT Jaipur
VLSI Curriculum in Indian Universities: An Analysis and Prescription