VDAT2000 Papers

	4^th VLSI Design And Test Workshops VDAT2000 August 25-27, 2000 The Habitat World, Lodi Road, New Delhi Please visit VSI publications for details on VDAT proceedings.
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	Test Physical Synthesis for Timing Convergence: Practice and Experience Jagdish Rao, Texas Instruments (India) System-level Testability Issues of Core-based System-On-Chip V. Ranganathan, RealChip SOC Methodologies: COSY P.Jayakumar, Philips Semconductors, Bangalore Testing Core-Based Systems Test Point Insertion in Core-based Designs at RTL VHDL Specifications D. Ravikumar, V. Meshram, and G. Mani, CRL, BEL (Bangalore) Optimization of IDDQ Test Architecture for Core-based Systems Rahul Kumar, IIT Delhi Verification A Scaleable Verification Environment for Complex SoC Designs Amitabh Menon, Jagdish Rao, Vaideeswaran S, Bharathi V, Texas Instruments (India) Testing in a VLSI Curriculum V.D. Agrawal. Bell Labs, USA Addressing Verification Bottlenecks using Equivalence Checkers Subhash Chandar G. and Vaideeswaran S., Texas Instruments (India) Synchronisation Techniques for Verification of Dual Execution Stream Processors Lakshmi Srinivasan, Sudhakar Surendran and Rubin A. Parekhji, Texas Instruments, India Test Generation Enhanced Mutual Testing Nitin Kakkar and C.P. Ravikumar, IIT Delhi Testing Asynchronous Squential Circuits using Synchronous Model M.C. Bhuvaneshwari and K. Shivanandam, PSG College of Technology Automatic Functional Pattern Generation for Verification of FSMs and Interacting FSMs Raghuram, Texas Instruments (India) Trends in Testing Scan Chain Reordering Vivek Agarwal et al., Texas Instruments (India) High-Speed VLSI Testing With Slow Test Application V.D. Agrawal, Bell Labs, Lucent Technologies, USA, Carlos G. Parodi, Lucent Technologies, NJ, USA, and Jason David, NJIT, USA Fault Grading for Functional Testing of Microprocessors Rajesh Kannah, ATI Tech. Design Methodologies A Methodology for Automation of Design Reuse Sacheendra Nath, Rupesh Shelar, and Jagmohan Nanaware, Silicon Automation Sysems Hierarchical Concurrent Flow Graphs for Analysis of Design Processes Vineet Sahula, IIT Delhi Exploring VLSI System Arhitectures Ajay Harikumar and Ashutosh Tiwari, Philips Semiconductors, Bangalore Hardware-Software Partitioning in a Reconfigurable Environment Puneet Gupta, Mindtree and Nitij Mangal, nVIDIA Performance Analysis Performance Modelling (YAPI-VCC-TSS-NAPA interfaces) Sirisha Voruganti, Philips Semiconductors, Bangalore Advances in Static Timing Analysis Savithri, Motorola India Electronics Ltd Characterizing A Flip-Flop Prashant Dubey, ST Microelectronics A methodolgy for high level behavioral modelling of DSPs Samvit Kaul and Suneel Kumar Reddy, Philips Semiconductors Low-power Software Power Optimizations in an Embedded System Vishal Dalal, Silicon Automation Systems Maximum Power Estimation Using Transition Fault ATPG Rakesh Babu Bobba, Jais Abraham and Rubin A. Parekhji, Texas Instruments, India Current Issues in Physical Design Integrated Crosstalk and Oxide Integrity Analysis in ASIC Designs P.R. Suresh, N.V. Arvind, Texas Instruments India, V. Sivakumar, Chandrani Pal, and Debaprasad Das Effect of Ionizing Radiation on the performance of NMOS inverter R.K. Chauhan, S. Dasgupta, and P. Chakrabarti. Banaras Hindu University Performance of Routability Driven FPGA Placement P. Kannan and D. Bhatia, University of Cincinnati Clock distribution networks Donepudi Narasayya and Srikant Reddy Modugula, ST Microelectronics Layout Tutorial Wirelength Minimization in Routing and Performance Enhancement in VLSI Design S. Sensharma and R. Pal, University of Calcutta Memory Design Design and development of Multiport memory generator Pratul Sharma, Amrish Kontu and Amit Bhansali, CRND, ST Microelectronics, India Design and Development Small Size memory in 0.18 Micron technology Dibya Dipti, Seema Jain, Nirmallya Kar, CRND, ST Microelectronics, India Ideas in Logic Design A New Synthesis of Symmetric Functions Debesh Das, Jadavpur University, H. Rahman, Jadavpur University, and B. Bhattacharya, ISI Calcutta Faster Modular Multiplication in Hardware Sacheendra Nath, Silicon Automation Systems Design and FPGA Implementation of Vector Quantization Circuit using VHDL Kamran Nabi Khan, Controlnet India

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