VDAT1999 Papers

	3^rd VLSI Design And Test Workshops VDAT1999 August 20-21, 1999 The Habitat World, Lodi Road, New Delhi Please visit VSI publications for details on VDAT proceedings.
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	Test Test Sequence Generation with Cellular Automata Prabir Dasgupta, Santau Chattopadhyay and I. Sengupta, IIT Kharagpur Test Simulation Flow for Mixed Signal ICs Amit Premy, Texas Instruments, India Testing of Asynchronous Circuits M.C. Bhuvaneshwari and S.N. Shivanandam, PSG College of Technology Design for Testability Design for Testability Issues. in VLSI Chip Design T. Ramesh, Philips Semiconductors, Bangalore, India Techniques for Improving Fault Coverage in Embedded Core Based Systems A.Bagwe and Rubin Parekhji, Texas Instruments, Bangalore, India Testing Memory Designs Srikanth Balasubramanian, Philips Semiconductors, Bangalore, India New Ideas in Testing Power-constrained Optimization of Test Plans Gaurav Chandra, Ashutosh Verma, C.P. Ravikumar, IIT Delhi Recursive Pseudoexhaustive Test Pattern Generation with Cellular Automata Prabir Dasgupta, Santanu Chattopadhyay, I. Sengupta, IIT Kharagpur Design Tradeoffs for Test of Embedded Cores N.Prasad, J.Abraham and R.A.Parekhji, Texas Instruments, India Verification On-chip characterization and Debugging methodology for high-speed embedded memories Anand Hardi, Anil Kalra, Balwant Singh, Santosh and Shamsi Azmi, ST Microelectronics Processor Emulation Design and Verification Rubin Parekhji, Texas Instruments (India) Ltd. A BIST for Detecting Multiple Stuck-open and Delay Faults by Transition Counts Hafizur Rahaman, Debesh K. Das, and Bhargab B. Bhattacharya VLSI Design Process Extended Signal Flow Graph Model for VLSI Design Processes Vineet Sahula, IIT Delhi System-level VLSI Design Experiences V. Srisha and Saif Khan, Philips Semiconductors, Bangalore, India Memory Design RTL Design of a Small Memory B. Suresh and Harinath, Texas Instruments (India) Ltd. Design and Results of a Hierarchical Megabit SRAM Compiler R. Varambally and Christophe Frey, ST Microelectronics Power-constrained Testing of Embedded SRAMs G. Sreenivas, Cypress Semiconductors Low-Power Digital Signal Processing A Methodology for Exploring Area-Delay-Power Space for DSP Mahesh Mehendale, Texas Instruments (India) Ltd Low Power Microarchitectures for Programmable DSPs Amitabh Menon, Texas Instruments (India) Ltd System Level Considerations in Realizing Low Power DSP Applications S.D. Sherlekar, Silicon Automation Systems Design Ideas Area-Efficient Digital Waveform Generators Rohit Sharma, Texas Instruments (India) Ltd Clock Generator Chip: Architecture/Design Issues Anil K. Gundurao and Kaushal, Cypress Semiconductors I/O Pad Design Pradeep Mandal, Philips Semiconductors, Bangalore, India Layout Optimization Efficient Algorithm for the Channel Inversion Problem S. Sahni. University of Florida Complex Triangle Elimination Problem and its Applications to VLSI Parthasarathi DasGupta, Indian Institute of Management Layout Algorithms for FPGA Dinesh Bhatia, University of Cincinnati. OH, USA Signal Integrity Crosstalk Estimation in VLSI Circuits S. Sankara Subramanian, ATI Tech, G. Rajagopalan, Analog Devices, and C.P. Ravikumar, IIT Delhi An approach towards Hierarchical Detection of ESD Errors in a Physical Layout Sabyasachi Nag and Ananth Somayaji, Texas Instruments (India) Ltd An Effective Methodology to Extract Parasitic from Layout C. Rajkumar and Sanjay Kulkarni, Texas Instruments (India) Ltd Optimization A Physical Layout Efficiency Checker with an Emhpasis on Die Area Reduction Ganesh Kamath and Preetham Kumar, Texas Instruments (India) Ltd Decomposition of Finite State Machines for Area, Delay Minimization Rupesh S. Shelar, Silicon Automation Systems, Madhav Desai and H. Narayanan, IIT Bombay Estimating the Deadline Miss Probability in Real Time Embedded Systems Shampa Chakraverty, Netaji Subhash Institute of Technology

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