VLSI Society of India

Illuminated Mysore Palace

VLSI Education Workshop

SJCE, Mysore

May 9 to 14, 2005

Sponsored by VLSI Society of India (http://vlsi-india.org/vsi)

Cosponsored by: IEEE-SSC/EDS Bangalore, IEEE-SJCE Mysore

Report:
Day-1: The workshop was inaugurated by Dr Karthik, Analog Devices who emphasized the need of such workshops. His keynote talk addressed the VLSI Design and the associated challenges. Dr Navakanta Bhat, Indian Institute of Science, conducted a tutorial on Custom VLSI Design Flow.
Day-2: Mr. Ramanujam spoke on Analog Circuit Design. Prof. K. Radhakrishna Rao, IIT Madras, gave a tutorial on Analog Design.
Day-3: Dr. C.P. Ravikumar, Texas Instruments India, gave a talk on CAD tools for VLSI Circuits. Mr. Ram Jonnavithula of Texas Instruments talked on Testing of Integrated Circuits and Design-for-Test. Mr. Bilas Dutta of Texas Instruments India spoke on the topic Physical Design Flows.
Day-4: Dr. J. Kuruvilla Verghese, CEDT, Indian Institute of Science gave a talk on FPGA Design using VHDL. Day-5: Dr. Ashok Rao, Indian Institute of Science gave a talk on DSP Architectures, Dr. C.R. Venugopal, SJCE, Mysore, gave a talk on computer architecture.

An intensive one-week workshop is being organized for faculty and postgraduate students of Indian organizations with the objective of exposing the participants to state-of-the-art in VLSI methodologies and design principles.  The technical program of the workshop includes tutorials from experts in the field, hands-on lab sessions, tool demonstrations, and discussion sessions. 

This is the third in the series of annual VLSI Design workshops being conducted at SJCE, Mysore. Please contact Prof. C.R. Venugopal, Department of Electronics and Communication, SJCE, Mysore 570006, Phone 0821 -2512568, 0821-2511383 for registration or a hardcopy brochure/registration form.

Agenda

The advance program of the workshops is available now:

• Agenda (PDF)

Workshop Organizer