VLSI Society of India

Amber Fort, Jaipur

VLSI Education Workshop

MNIT, Jaipur

March 8-12, 2005

Sponsored by VLSI Society of India (www.vlsi-india.net/vsi)

Cosponsored by: MNIT, Jaipur and IEEE Delhi Section

Report:
Day-1: Prof. R. Sharan of LNMIIT Jaipur inaugurated the workshop. Prof. M. Balakrishnan of IIT Delhi delivered a talk on Application-Specific Instruction Processors. Dr. Kolin Paul of IIT Delhi delivered a talk on Designing with FPGA platforms- Challenges and opportunities. Dr. Manoj Jain of Egineering College (Udaipur) talked on ASIP Design Space Exploration, followed by talks on Behavioral Synthesis and high level test synthesis by Dr. M. S. Gaur (MNIT, Jaipur), System-on-package by Dr. S. K. Bhatnagar (MNIT, Jaipur), and Layout design & Circuit simulation by Dr. S. C. Bose of CEERI Pilani.
Day-2: Prof. D. Nagchoudhuri of DA-IICT, Gandhinagar, delivered talks on CMOS Analog IC and IC Manufacturing. Megha Chaitanya of ST-Microelectronics discussed Programmable hardware & software platforms. Two lab sessions were organized on CMOS Circuit simulation and Layout design.
Day-3: Prof. C. R. Venugopal of SJCE Mysore discussed VLSI architectures for DSP. Mr. Sanjay Chakravarty of CoWare presented a talk on Embedded Software development in the Platform context. Mr. Deepak Sabharwal of Virage Logic talked about Memory Compilers. Mr. Pranav Joshi delivered a talk on HVLs in SoC verfication followed by a talk from Dr. Atanendu Mandal of CEERI Pilani on Designing an Embedded Processor: Specifications to Implementation. Dr. V. Sahula of MNIT Jaipur delivered a talk on Logic optimization and Technology mapping.
Day-4: Dr. Chandrashekhar, Director, CEERI Pilani, delivered a talk on VLSI Design Methodology: Traditional Approaches and Digital Circuit Verification & Simulation. It was followed by a talk on Semiconductor Device Modeling by Prof. S. Sancheti of MNIT Jaipur. Two lab sessions, one on HDL based verification and another on FPGA implementation, were held in the afternoon. The CAD tools used in the course included the HDL simulator & FPGA synthesis tool from Mentor Graphics, Layout design and simulation tool from Tanner Inc.
Day-5: C. P. Ravikumar of Texas Instruments delivered two talks on Design for testability, with emphasis on techniques for test data volume reduction. This was followed by a talk by Mr. Shishir Gupta of Cadence on Creating nanometer electronics profitably. Mr. D. Boolchandani of MNIT Jaipur delivered a talk on Analog Synthesis approaches.

An intensive one-week workshop is being organized for faculty and postgraduate students of Indian organizations with the objective of exposing the participants to state-of-the-art in VLSI methodologies and design principles.  The technical program of the workshop will include tutorials from experts in the field, hands-on lab sessions, tool demonstrations, and discussion sessions.

Advance Programme

The advance programme is now available in PDF format:

• Advance Programme



• Registration form

Program Committee

Organizing Committee