VLSI Society of India
A Two-day Workshop on
VLSI Signal Integrity
December 16 17, 2005
Hotel Atria, Bangalore
Organized by VLSI Society of India
In cooperation with IEEE Circuits and Systems Society
Bangalore Chapter
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VLSI Society of India
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A Two-day Workshop onVLSI Signal IntegrityDecember 16 17, 2005 Hotel Atria, Bangalore Organized by VLSI Society of India In cooperation with IEEE Circuits and Systems Society Bangalore Chapter |
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As VLSI technology scaling continues, designers have to deal with problems of signal integrity. Capacitive cross-coupling between adjacent wires can lead to glitches and/or delay variations. Simultaneous switching of signals in the circuit can lead to power integrity problems. Precautions are necessary to ensure that signal integrity problems do not lead to failures during circuit operation. Over the past decase, EDA tools and design flows have evolved to deal with signal integrity problems. This workshop will deal with various aspects of signal integrity and provide both a tutorial overview as well as an industrial perspective of the problem.
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Day - 1 |
December 16, 2005 |
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08.30 AM 09.15 AM |
Registration |
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9.15 AM 9.30 AM |
Inauguration |
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9.30 AM 9.45 AM |
Opening Remarks Dr Ram Achar, Carleton University, Canada |
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09.45 AM 11.00 AM |
Session I: Introduction to Signal Integrity Problems in DSM - An Industry Perspective Speaker: Dr. Ashok Balivada, Analog Devices, India. |
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11.00 AM 11.30 AM |
Coffee Break |
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11.30 AM 01.00 PM |
Session II: Circuit Extraction (Dr. Shabbir Batterywala, Synopsys, India) |
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01.00 PM 02.00 PM |
Lunch |
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02.00 PM 03.30 PM |
Session III: Review of Circuit Simulation (Dr. Ram Achar, Carleton University) |
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03.30 PM 04.00 PM |
Coffee Break |
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04.00 PM 05.30 PM |
Session IV: Static Timing Analysis with Signal Integrity (Arvind, Texas Instruments, India) |
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Day - 2 |
December 17, 2005 |
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08.30 AM 09.30 AM |
Registration |
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09.30 AM 11.00 AM |
Session V: Transmission Line Interconnects, SPICE Macromodels and comparative study of industry tools for signal integrity (Dr Ram Achar, Carleton University) |
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11.00 AM 11.30 AM |
Coffee Break |
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11.30 AM 01.00 PM |
Session VI: Signal Integrity Issues in Design For Test (Dr. C.P. Ravikumar, Texas Instruments, India) |
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01.00 PM 02.00 PM |
Lunch |
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02.00 PM 03.30 PM |
Session VII: Measurements, Multiport Parameters and scattering parameter based macromodels for circuit analysis (Dr Ram Achar, Carleton University) |
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03.30 PM 04.00 PM |
Coffee Break |
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04.00 PM 05.30 PM |
Session IV: Panel Discussion on Signal integrity Challenges Ahead. Experts will discuss the challenges in the area of Signal Integrity. Names of the panelists will be announced. |
Course Fee |
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Before November 1, 2005 |
After November 1, 2005 |
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Industry Members (Non-Members) |
Rs. 3000/- |
Industry Members (Non-Members) |
Rs. 4000/- |
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VSI/IEEE members |
Rs. 2500/- |
VSI/IEEE members |
Rs. 3500/- |
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Academic/governmental organizations from India (Non-members) |
Rs. 1500/- |
Academic/governmental organizations from India (Non-members) |
Rs. 2000/- |
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Academic/governmental organizations from India (Members of VSI/IEEE) |
Rs. 1000/- |
Academic/governmental organizations from India (Members of VSI/IEEE) |
Rs. 1500/- |
Speakers:
| Dr. Ram Achar obtained his M.E. from BITS, Pilani and Ph.D. from Carleton University, Canada. He is currently an Associate Professor at Carleton University. He has published a large number of papers in International Conferences and Journals. He is the author of six books, including Introduction to High-Speed Circuit and Interconnect Analysis. He is the recipient of several best paper awards. |
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Arvind is Member, Group Technical Staff at Texas Instruments, India. He has led the development of in-house flows for crosstalk delay calculation at TI. His areas of interest include Signal Integrity, Physical Design, and Statistical Timing Analysis. |
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Dr. Ashok Balivada graduated from IIT-Bombay and did his Doctorate from the University of Texas at Austin. His area of interest is Design and Testing of VLSI systems. Currently he is Design Manager at Analog Devices, India. |
| Dr Shabbir Batterywala obtained his Ph.D. degree from IIT Bombay. He is currently part of the Advanced Research Group at Synopsys, India. His research interests are in the areas of Signal Integrity, Circuit Extraction, and Physical Design. He has published a large number of papers in international conferences and journals. |
| C.P. Ravikumar is with Texas Instruments India as a Senior Technologist in VLSI Test. Before joining TI, he served on the faculty of the Department of Electrical Engineering at IIT Delhi as a Professor. He has published over 200 papers in International conferences and journals. He is the recipient of best paper award (VLSI Design conference) and best student paper award (VLSI Design conference). He is a senior member of IEEE, Fellow of the Indian Microelectronics Society, and current secretary of VSI. |
The registration form can be downloaded from here:
Information flyer and registration form (PDF Format)
