VLSI Society of India

In cooperation with

IEEE Circuits and Systems Society (Bangalore Chapter)

is happy to announce

A Two Day Workshop

On

Recent Advances in Memory Technology,

Design and Test

Venue - Hotel Central Park, Manipal Centre, M. G. Road, Bangalore

Date - Jan 10-11, 2005

Speakers:

Sreedhar Natarajan is currently a Director for embedded Memory development at MoSys Incorporated, Ottawa, CANADA. He was a Member, Group Technical Staff, at Texas Instruments, Dallas, where he worked on the design and development of SRAMs, DRAMs, and FeRAMs.  He also held the position of Design Manager responsible for SRAM development at Paradigm Technologies, Santa Clara, CA. His interests are low power and high speed memory designs.  Sreedhar Natarajan serves on various international conference committees like ISSCC, CICC and VLSI Symposium and also serves on the IEEE Standards board. He currently serves on the technical advisory council for many universities on memory related projects and an adjunct member of faculty at University of North Carolina, Charlotte. He has been an invited speaker at various IEEE international conferences.He is the recipient of the IEEE Circuits and Systems Outstanding Service Award'01 and the past chairman for the Dallas Chapter of the IEEE-Solid State Circuits.  He co-authored the book "SOI Design: Analog, Memory and Digital Design -Dec 2001, Kluwer Academic Publishers". He is currently authoring the book titled "CMOS Practical Memory Design". Sreedhar has 15 publications and over 20 filed and issued patents to his credit. He is a senior member for the Institute of Electrical and Electrical Engineers.

Katsuyuki Sato joined Hitachi Ltd. in 1976 just after graduated from Electrical Engineering of Kyushu University, Fukuoka, Japan.   Since then, he has been working for DRAM circuit design and its development.   In October, 2000, he was transferred to Elpida Memory Inc. which was established   then by merging DRAM divisions of Hitachi and NEC. Currently, he works for technical marketing and system evaluation as a general manager at Elpida Memory Inc. He also received MS degree from Ohio State University, Ohio, USA in 1983,   and Ph.D. from Kyushu University , Fukuoka, Japan in 1998, respectively. Dr. Sato currently is a senior member of IEEE, and a chair of the memory subcommittee of ISSCC.

Dr Nilanjan Mukherjee is with Mentor Graphics, USA as an Engineering Manager in the Design, Verification and Test, where he focuses on developing next generation test methodologies for DSM designs, test synthesis, test compression, memory test, and fault diagnosis. Prior to joining Mentor Graphics, Dr. Mukherjee worked at Lucent Bell Laboratories in Princeton, New Jersey, where he primarily contributed in the areas of Logic BIST, RTL testability analysis, path-delay testing, and on-line testing. He has co-authored more than 30 technical articles in leading IEEE journals and conferences. He is also a co-inventor for 9 US patents. Nilanjan was the recipient of the Best Paper Award at the 1995 VLSI Test Symposium. He co-authored a paper that received the Best Student Paper Award at the Asian Test Symposium in November 2001. Dr. Mukherjee has reviewed papers for numerous IEEE journals and conferences. He also served as a member of the technical program committee for DDECS 2003. Nilanjan has given invited talks at numerous companies and universities in USA and India. He also delivered tutorials on DFT at major international conferences and delivered DFT seminars organized by Mentor Graphics at various locations in USA and India.

C.P. Ravikumar is with Texas Instruments India as a Senior Technologist in VLSI Test. Before joining TI, he served on the faculty of the Department of Electrical Engineering at IIT Delhi as a Professor. He has published over 150 papers in international conferences and journals. He has served as the technical program chair for VLSI Design Conference and the VLSI Design and Test Workshops. He has also served as the member of the program committee for several conferences, including HiPC. He is the recipient of SIGDA student scholarship award, best paper award (VLSI Design conference) and best student paper award (VLSI Design conference). He is a senior member of IEEE, fellow of the Indian Microelectronics Society, and current secretary of VSI.

Other speakers are expected to participate. Updates will be announced on VSI Website.

Program:

Day 1

 Day 2

Registration Details:

A draft/cheque should be made out to “VLSI Society of India” and must be sent to Mr Mohan Kumar, Finance, VLSI Society of India, Texas Instruments India, Bagmane Tech Park, CV Raman Nagar, Bangalore 560093. Please include your name, e-mail address, contact address, phone and FAX numbers, and professional status.

Queries about the tutorial must be sent to Dr C.P. Ravikumar, Secretary, VSI, ravikumar@vlsi-india.org.

More details about local arrangements will become available on the website http://vlsi-india.org/vsi/ - please watch this page regularly.