VLSI Society of India,

IEEE Circuits and Systems Society (Bangalore Chapter),

and

IEEE Electron Devices and Solid State Circuits Society (Bangalore Chapter)

are happy to announce

A TWO-DAY WORKSHOP

ON

LOW POWER DESIGN TECHNIQUES

Venue – Indian Institute of Science, Bangalore

Date – Feb 25-26 (Friday-Saturday)

Time – 9.00 – 6.00 PM

SPEAKERS

Prof. Eric A. VITTOZ : Prof. Vittoz is an IEEE Fellow and has published more than 100 papers and holds 25 patents.He has been with the Centre Electronique Horloger S.A. (CEH), Neuchâtel,  where he participated in the development of the first prototypes of electronic watches. He was the Vice-Director of CEH, supervising advanced developments in electronic watches and other micropower systems. Later, he took the responsibility of the Circuits and Systems Research Division of the Swiss Center for Electronics and Microtechnology (CSEM) in Neucâtel, where he was appointed Executive Vice-President, Integrated Circuits and Systems. He is also directly responsible for the Advanced Research section of CSEM. His field of personal research interest and activity is the design of low-power analog CMOS circuits, with emphasis on their application to advanced perceptive processing. Since 1975, he has been lecturing and supervising undergraduate and graduate student projects in analog circuit design at EPFL, where he became Professor in 1982.

Prof. Christian Piguet. Prof. Piguet joined the Centre Electronique Horloger S.A., Neuchâtel, Switzerland, in 1974. He worked on CMOS digital integrated circuits for the watch industry, low-power embedded microprocessors and CAD tools based on a gate matrix approach. Prof. Piguet is now Head of the Ultra-Low-Power Sector at the CSEM (Centre Suisse d'Electronique et de Microtechnique S.A), Neuchâtel, Switzerland. He is presently involved in design and management of low power and high speed integrated circuits in CMOS technology. His main interests include design of very low-power microprocessors, low-power standard cell libraries, gated clock and low-power techniques as well as asynchronous design. He is Professor at the Ecole Polytechnique Fédérale Lausanne (EPFL), Switzerland, he also lectures in VLSI and microprocessor design at the University of Neuchâtel, Switzerland, as well as other postgraduate courses in low-power design.

Dr. Kiyoo ITOH has been leading RAM technology at Hitachi Ltd: He was the lead designer of the first prototype for eight generations of Hitachi DRAMs ranging from 4Kb to 64Mb. He initiated circuit inventions and developments to reduce sub-threshold current of MOSFETs even for the active mode, which is highlighted today in low-voltage CMOS LSI design. Typical examples of the reduction circuits are the dynamic substrate back-bias control, multi-threshold (Vt) CMOS logic, various gate-source (self) back-biasing schemes, and power switch that we take for granted today. He holds over 370 patents in Japan and US. He authored three books and one book chapter on memory designs, and contributed over 130 technical papers and presentations, many of them invited, in IEEE journals and conference proceedings. Dr. Itoh has won 16 honors in US, Europe, and Japan. They include the IEEE Paul Rappaport Award in1984, the Best Paper Award of ESSCIRC90, and the 1993 IEEE Solid-State Circuits Award. He is an IEEE Fellow. In Japan, his awards include the National Invention Award (Prize of the Patent Attorney's Association of Japan) in 1989, the Commendation by the Minister of State for Science and Technology (Person of Scientific and Technological Merits) in 1997, and the National Medal of Honor with Purple Ribbon in 2000.

V. Ramgopal Rao is an Associate Professor in the Department of Electrical Engineering, IIT Bombay. He has over 140 publications in these areas in refereed international journals and conference proceedings and holds two patents. Prof. Rao is an Editor for the IEEE Transactions on Electron Devices in the CMOS Devices and Technology area and is a Distinguished Lecturer (DL), IEEE Electron Devices Society. He is a Senior Member, IEEE and a Fellow, IETE. Dr. Rao received the Swarnajayanti Fellowship award for 2003-2004, instituted by the Department of Science and Technology, Govt. of India. He is also a working group member setup by the Govt. of India on Nanotechnology. Prof. Rao was the organizing committee chair for the 17th International Conference on VLSI Design, and was Chairman, IEEE AP/ED Bombay Chapter during 2002-2003.

Dr C. Srinivasan has been leading mixed signal and analog design projects at Texas Instruments, India for several years. He is currently working on aspects of power management in system-on-chip designs.

Other speakers are expected to participate. Updates will be announced on VSI Website.

Click here for PDF version of this program.

Program:

Day 1 – Low-Power Analog Design

Day 2 – Low-Power Digital Design

Registration Details

Draft/Cheque should be made out to “VLSI Society of India” and must be sent to Mr Mohan Kumar, Finance, VLSI Society of India, Texas Instruments India, Bagmane Tech Park, CV Raman Nagar, Bangalore 560093. Please include the participant’s name, e -mail address, contact address, phone and FAX numbers, and professional status. Write “Low Power Workshop, Feb 2005” on the top of the application form and behind the draft. Clearly indicate the name(s) of the participant(s) if you are sending bulk registrations from the same organization. The registration fee includes registration material and lunch/tea on the day(s) for which you have registered.  You are responsible for making your own arrangements for stay and travel. Receipts for the payment and participation certificates will be made available at the workshops. The number of participants will be limited; send your registrations to reach before Feb 10, 2005.  Confirmations will be sent by email only. Queries about the tutorial must be sent only to lpd05@hotmail.com . 

Venue Information – The Indian Institute of Science is located near Malleshwaram/Yeshavantpur in Bangalore.  The approximate distance from the Railway station is about 5 km, and from the Airport is about 15 km. The locals refer to IISc as “Tata Institute”.  The weather in Bangalore during February is pleasant and nights are chilly.