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VLSI Society of India
www.vlsi-india.org/vsi |
Electronic System Level Design Workshop,
2006
January 9-10, 2006
Bangalore,
India
Venue: Golden Jubilee Seminar Hall,
Department of Electrical Communication
Engineering,
Indian Institute of Science, Bangalore
VSI Home VSI Events
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IEEE Circuits and Systems Society,
Bangalore Chapter
www.ieee.org 
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| ESLD - 2006: Workshop
Goals
Raising the level of abstraction to electronic system-level is emerging as a power solution to the problem of design productivity. ESL Design encompasses a number of disciplines, such as system system-level design entry, translation of high-level language descriptions to RTL, hardware-software partitioning, system-level verification, and system-level testing. A number of commercial products and associated methodologies are emerging for ESL Design. The goal of the workshop is
to bring together a number of practitioners in the area of ESL Design and create a forum for exposing and discussing these methodologies. |
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The workshop will consist of keynote talks, invited
presentations, embedded tutorials, exhibits, and a panel
discussion.
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Agenda:
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Day 1: January 9, 2006 |
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08.30 AM |
Registration |
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09.00 AM |
Inauguration |
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09:15 |
Curtain Raiser |
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09:30 AM |
Keynote 1 - Prof. Arvind, Massachusetts Institute of
Technology |
How
future systems may be designed |
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10:30 AM |
Tea |
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11:00 AM |
Keynote 2 - Prof. Rajesh Gupta, UCSD |
ESL: A Crucial Enabler for Platform Ownership |
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12:00 NN |
Nagendra Gulur Dwarakanath, Texas Instruments, India |
System-level Design - Practice and Experience |
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12:45 PM |
Viswanath Chakarala, Specialist, VLSI Systems Design,
Wipro Technologies |
System C Modeling Approach for SoC Development |
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01.30 PM |
Lunch |
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02.30 PM |
Sarang Shelke, Director - Technology, Poseidon Design
Systems |
Processor Based System Performance Acceleration: An ESL
Approach |
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03.15 PM |
Sanjay Chakravarti, Sr. Manager, IP and Services, CoWare |
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04.00PM |
Tea |
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04.30 PM |
Badri Gopalan, Ageia, India |
System Verilog - An Overview |
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05.30 PM |
Srinivasan Venkataraman, Synopsys India |
System-level Verification using System Verilog |
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06.00 PM |
End of Day 1 |
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Day 2: January 10, 2006 |
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08.30 AM |
Registration |
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09:00 AM |
Keynote 3 - Brian Bailey, Former Chief
Technologist, Mentor Graphics and Member of
Technical Advisory Board, Poseidon Design Systems |
"ESL? What is that?" |
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10.00 AM |
Tea |
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10.45 AM |
Keynote 4 - Rishiyur Nikhil, CTO, BlueSpec |
A
Technical
Introduction to ESLD with Bluespec System
Verilog |
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12.15 PM |
Raghu Tupuri, AMD
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Systems level design space exploration
Performance
Modeling |
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01.00 PM |
Lunch |
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02.00 PM |
Himanshu Sanghavi, Project Manager, Tensilica
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ESL Requirements for Multiprocessor SoC Design using
Configurable
Processors |
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02:45 PM |
Bill Salefski, VP - Technology, Poseidon Design Systems |
"ESL :
Why Now?" |
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03:30 PM |
Tea |
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04.00 PM |
Panel Discussion : "ESL - Dream or Reality?" |
Ravi Janak, CEO and President, Poseidon Design
Systems |
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Shiv Tasker, CEO, BlueSpec |
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M. Balakrishnan, IIT Delhi |
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Moderator: Brian Bailey |
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06.00 PM |
End of Day 2 |
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Organizing Committee:
C.P. Ravikumar, Texas Instruments, India
Suhas Hiwale, Poseidon
Design Systems, Bangalore, India
Subodh Patil, Poseidon
Design Systems, Bangalore, India
S. Jagannathan, Infineon, Bangalore,
India
Bharadwaj Amruthur, Indian Institute of Science,
Bangalore, India
Maria Adolf, Bluespec, Germany
Alok Kumar, Coware, Noida,
India
Ashish Dixit, Tensilica, India
A. Vasudevan, Wipro Technologies,
Bangalore, India
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Registration Fees:
Workshop Registration Fees
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Before December 15, 2005 |
After December 15, 2005
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Professionals (Non-Members) |
Rs. 3,500/- |
Professionals (Non-Members) |
Rs. 4,500/- |
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Professionals (VSI/ IEEE members) |
Rs. 3,000/- |
Professionals (VSI/ IEEE members) |
Rs. 4,000/- |
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Students/ Faculty (Non-members) |
Rs. 2,500/- |
Students/ Faculty (Non-members) |
Rs. 3,500/- |
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Students/ Faculty (VSI/ IEEE members) |
Rs. 2,000/- |
Students/ Faculty (VSI/ IEEE members) |
Rs. 3,000/- |
Click here to get the registration form for ESLD 2006 workshops:
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