VLSI Society Of India : 2nd Workshop on Design Verification Methodologies

Nanotechnologies have ushered in System-On-Chip designs with 50 million gates. Functional and timing verification of such designs is a formidable task. Design Verification has been known to be biggest contributor to the design cycle time. Statistics also indicate that design respins are often due to functional bugs detected late. Cutting down the time for verification is one of the major goals of design teams across the globe. Many new methodologies have emerged towards solving this problem. This two-day workshop is intended as a forum to discuss the new trends and methodologies for Design Verification. It is also a forum to share current practices in Design Verification. The workshop is suitable for practitioners of Design Verification and for students/faculty who are engaged in VLSI design projects.

Day 1 : March 24, 2006	Venue: Platinum Gallery Hall, Tower 3
08.30 AM – 09.00 AM	Registration
09.00 AM – 09.15 AM	Inauguration
09.15 AM – 10.30 AM	A. Vasudevan, Wipro Technologies, Bangalore Keynote Presentation - “Design Excellence : Challenges in Deep-submicron Technologies” Vasudevan A is the Vice President and head of the VLSI/System Design Division of Wipro Technologies. He has an extensive experience in design and management of system design and SoC projects. In a career spanning twenty years at Wipro, Vasudevan was responsible for making its VLSI/ System design group a leading vendor providing SoC (System on Chip) and system design services to customers. Vasudevan is an MTech from the Indian Institute of Technology (IIT), Kanpur.
10.30 AM – 11.00 AM	Tea Break
11.00 AM – 12.00 NN	Raj Mitra, Texas Instruments, Bangalore “Industrial Practices in Verification” Dr Mitra received his BTech and PhD degrees in Computer Engineering from IIT Kharagpur. He has over 15 years of experience in different fields of EDA, including synthesis, verification, power analysis, and embedded systems design. He had been working with Cadence and Synopsys, in their synthesis and verification R&D groups, and in CMC Ltd, in their Image Processing and Pattern Recognition group. He is now leading the EDA team at Texas Instruments Bangalore, and is also coordinating the deployment of Formal Verification tools in different sites of TI.
12.00 NN – 1.00 PM	Muralidhar Bolisetty, Synopsys, Bangalore “Static Verification - The Future Functional Verification” Muralidhar Bolisetty has over 10 yrs of experience in various facets of digital hardware design & verification of boards, thick film hybrid microcircuits, FPGA's and hi-performance ASICs. Last 5 years, he was primarily involved in functional verification and verification methodologies for microprocessors and network processors. He is an EE graduate from BITS-Pilani and is currently working as Staff Verification Solutions Engineer with Synopsys India.
01.00 PM – 02.00 PM	Lunch
02.00 PM – 03.00 PM	Venkatesan Swaminathan, Intel, Bangalore “An Environment for Executing Full Chip Pre-Silicon Environment on Post-Silicon” Vekatesan Swaminathan has several years of industry experience in design verification, test generators for pre silicon and post silicon environments. His interests are in validation environments for today's networking and processor platforms and building pre silicon environments, which can be reused for post silicon testing. He has published papers in various forums like IPSOC.
03.00 PM – 04.00 PM	Ms. Deepali Maydeo, Tensilica, Pune “Verification on User Defined Processor Extensions” Ms Deepali Maydeo is currently working with Tensilica India as Manager-TIE verification and has around 9 years of experience in verification. Her interests are in working on innovative and effective verification methodologies.
04.00 PM – 04.30 PM	Tea Break
04.30 PM – 06.00 PM	Dr Shankar Balachandran, IIT Madras “Digital Design Verification” Shankar Balachandran is currently an Assistant Professor in the Computer Science and Engineering Department at IIT-Madras. He received his Bachelors in Computer Science and Engineering from University of Madras and Ph.D. in Electrical Engineering from the University of Texas at Dallas. His area of interests are in CAD tools for VLSI, reconfigurable computing and computer architecture.
End of Day 1

Day 2 : March 25, 2006	Venue: Sapphire, Tower 3
08.30 AM – 09.00 AM	Registration
09.00 AM – 10.00 AM	Subir K Roy, Texas Instruments, Bangalore “Formal Verification – Industrial Practices” Subir K. Roy got his B.E., M.Tech. and Ph.D. degrees from University of Pune, IIT Madras and IIT Bombay in 1982, 1984 and 1993, respectively. Prior to 1993 he worked in Semiconductor Complex Limited, Chandigarh and VLSI Design Centre, IIT Bombay. From 1993 to 2001 he was with the faculty of Electrical Engineering, IIT Kanpur. From 2001 to 2003 he was with Synplicity Inc, Sunnyvale USA & Bangalore. Since 2004 he has been working with Center of Excellence, System on Chip, Texas Instruments India, Bangalore. He spent 2 years from 1998 to 2000 carrying out research on formal verification in Fujitsu Laboratories Limited, Kawasaki, Japan, on a sabbatical from IIT Kanpur. His research interests are in formal verification, power estimation and CAD for VLSI.
10.00 AM – 10.30 AM	Tea Break
10.30 AM – 11.00 AM	Shailesh Dave, eInfochips Ltd, Pune “Assertion Based Verification” Shailesh Dave is project manager for ASIC design & Verification Group at eInfochips Ltd. He has over 5 years of experience in chip design and Verification. Shailesh holds bachelor’s degrees in electronics and communications. He started his career in chip design as a verification engineer. He has worked as Design and Verification engineer for designs like PCI Express, graphic designs, DSP blocks, UMTS based receivers using High-Level Verification Languages, Assertions and emulators like Palladium.
11.00 AM – 12.00 NN	Vinaya Singh, Cadence Design Systems, Noida “Is Formal ABV Usable for Real Verification?” Vinaya Singh is M.Tech in computer science from IIT Bombay and has over 10 years of experience in EDA product developments in the area of verification and synthesis. Vinaya is member of Accellera OVL committee and was task leader of IEEE VHDL synthesis standard 1076.6-2004. Vinaya holds two patents in the area of formal verification. Currently he is working as Senior Member of Consulting Staff at Cadence Noida R&D facility.
12.00 NN – 01.00 PM	Lunch
01.00 PM – 02.00 PM	Mahesha Puttanna and Sunil Vishwanathan, Wipro Technologies “SystemC Models in Design Verification” Mahesha Puttanna is verification lead and a consultant at Wipro technologies with 8 years of experience in ASIC Verification. He has been instrumental in developing verification methodology for complex ASICs that has consistently delivered first silicon success. He has developed test benches using languages like Verilog, VHDL, Vera and Specman. Mahesha earned his M. Tech from Sri Jayachamarajendra college of engineering, Mysore. Sunil Viswanathan is a Modeling lead and a consultant at Wipro Technologies with many years of experience in designing and developing software models for various processors and peripherals.
02.00 PM – 03.00 PM	Amit Sharma, Synopsys, Bangalore “Improving Verification Productivity with SystemVerilog” Amit Sharma has around 5 years of experience in various facets of functional verification of networking chips and protocol, microprocessors and system level platforms. During the last few years, he has been primarily involved in testbench and simulation technologies and the deployment of the same across various designs. He is an EE graduate from REC, Surathkal and is currently working as Lead Verification Solutions Engineer with Synopsys India.
03.00 PM – 03.30 PM	Tea Break
03:30 PM – 04.30 PM	Discussion
04.30 PM – 05.00 PM	Conclusions

Complete information and the registration form regarding this workshop can be downloaded in the form of a PDF document:

Since the workshop venue is the campus of Wipro Technologies, we need to work with the Security personnel of Wipro to make the process of entering the campus and registering a smooth one.

Please follow the rules and regulations given below. Your cooperation in this regard is appreciated.

The registration fee includes registration material, lunch and refreshments. Transport and stay arrangements are the responsibility of the participants. Registration can be transferred to a colleague if intimation is provided 15 days before the event. Processing fee of Rs500/- will be charged against cancellation of registration.

Please note that the seats are limited; and we have stopped accepting any new registrations for this workshop. If you have already sent us a registration form along with a DD, you will must have received the confirmation email from VSI Secretariat.

The first workshop in this series was held on November 25, 2005 at Hotel Atria, Bangalore and was attended by about 60 professionals. The details of the previous workshop can be found at: DVM 2005

The Pune Development Centre of Wipro Technologies is located in phase I of Rajiv Gandhi Infotech Park, Hinjewadi, Pune, and is 25 kms from the heart of Pune city. Pune city, a major railway junction, is easily accessible by air, train, and bus. Pune and Mumbai are well connected by the express highway.

The workshop will be conducted at the Learning Centre located in the campus of Wipro Technologies, Pune.

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Corporate Sponsor:

Venue: Platinum Gallery Hall, Tower 3

After February 28, 2006