|
Four Day Intensive Course On Design for Testability - Theory and Practice July 27-30, 2005 Bangalore
|
||||||||||||||||||||||||||
|
Call For Participation VLSI Society of India announces a 4-day intensive course on "Design for Test - Theory and Practice" taught by Prof. Adit Singh and Prof. Vishwani Agrawal of Auburn University during July 27-30, 2005. The venue will be in Bangalore. If you need softcopy or hardcopy of the registration form, write to vsisecy@vlsi-india.org. After completing the registration form, mail it with the DD to the following address.
Please make the DD to VLSI Society of India payable at Bangalore. On the back of the DD, please write DFT Course. Partial registration is not permitted. Registration is not transferable. Queries may please be sent to: vsisecy@vlsi-india.org
Instructors
Adit D. Singh is James B. Davis Professor of Electrical & Computer Engineering at Auburn University, where he directs the VLSI Design & Test Laboratory. Earlier he has held faculty positions at the University of Massachusetts in Amherst, and Virginia Tech in Blacksburg. His research interests are in VLSI design, test, and reliability, and he has published extensively in these areas. Over the years he has taught approximately 50 short courses in-house for companies including IBM, National Semiconductor, TI, AMD, Bell Labs and Sandia Labs (earlier also for Digital, Control Data, and Data General), and at IEEE technical meetings, and through university extension programs. These have primarily been in the areas of VLSI design, test, reliability and fault tolerance. Prof. Singh currently serves on the Executive Committee of the IEEE Test Technology Technical Council, on the Editorial Board of IEEE Design and Test, and is the General Chair of the 2003 IEEE Memory Test Workshop. He is a Fellow of IEEE and a Golden Core Member of the IEEE Computer Society.
Vishwani D. Agrawal is James J. Danaher Professor of Electrical & Computer Engineering at Auburn University, Auburn, Alabama, USA. He has over thirty years of industry and university experience, working at Bell Labs, Rutgers University, TRW, IIT in Delhi, EG&G, and ATI. His areas of research include VLSI testing, low-power design, and microwave antennas. He has published over 250 papers, holds thirteen U.S. patents and has co-authored 5 books including Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits with Michael Bushnell at Rutgers. He is the founder and Editor-in-Chief of the Journal of Electronic Testing: Theory and Applications, was a past Editor-in-Chief of the IEEE Design & Test of Computers magazine, and is the Founder and Consulting Editor of the Frontiers in Electronic Testing Book Series. Dr. Agrawal is a co-founder of the International Conference on VLSI Design, and the International Workshops on VLSI Design and Test, held annually in India. He served on the Board of Governors of the IEEE Computer Society in 1989 and 1990, and, in 1994, chaired the Fellow Selection Committee of that Society. He has received seven Best Paper Awards, the Harry H. Goode Memorial Award of the IEEE Computer Society, and the Distinguished Alumnus Award of the University of Illinois at Urbana-Champaign. Dr. Agrawal is a Fellow of the IETE-India, a Fellow of the IEEE and a Fellow of the ACM. He has served on the advisory boards of the ECE Departments at University of Illinois, New Jersey Institute of Technology, and the City College of the City University of New York.
Course Contents
Course Fee Course fee includes registration material, lunch and refreshments on all the days. Transport and stay arrangements are the responsibility of the participants. Processing fee of Rs 1000/ - will be charged against cancellations.
|
||||||||||||||||||||||||||