Short Term Intensive Course on DFT for Digital Design, Hyderabad

Course details ... Registration form
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Short Term Intensive Course on DFT for Digital Design

4^th–6^th September 2006

VNR Vignana Jyothi Institute of Engineering and Technology, Hyderabad

www.vnrvjiet.ac.in
Download announcement (pdf)

Sponsored by:

VLSI Society of India

vlsi-india.org/vsi

“To contribute and promote the advancement of all aspects of VLSI technology, primarily in India”
Organized by

Dept of ECE, VNR-VJIET, Hyderabad

www.vnrvjiet.ac.in

“To develop as an institute of excellence to train human resources to international standards in the areas of Engineering and Technology”

Co-ordinators:

Prof. C.D. Naidu

HOD

Dept of ECE

M. Srinivasa Rao

Associate Professor

Dept of ECE

N.Balaji

Associate Professor

Dept of ECE

Course Resource persons:

C.P. Ravikumar, Senior Technologist, Texas Instruments, India

Ram Jonnavithula, Project Manager, DFT, Texas Instruments, India

Jais Abraham, Head-Technology, InnoDes Solutions Pvt. Ltd.

Course Contents:

What is VLSI Testing and why is required?

Test Process, different types of test, ATE

Economics of Testing and concepts of Yield

Fault models and Combinational Testing

ATPG - D algorithm

Podem Fault Simulation

Sequential Testing

Time-frame expansion technique

Testability - controllability and observability

Motivation for DFT - Scan-based test Boundary Scan Delay Testing

Reliability Testing - IDDQ and Burn-in Memory Testing

Built-in Self-Test Logic

BIST and Test Compression

Design for Test - area and performance considerations

System-level Testing.

Hands-on experience on Mentor EDA Tools

DFT Advisor

Fast Scan

Course Duration: 4 - 6 September 2006.

Target audience: Faculty Members from Engineering Colleges, students and professionals from the Industry.

The “Valluripalli Nageswara Rao (VNR) Vignana Jyothi Institute of Engineering and Techonology” Sponsored by “VIGNANA JOTHI”, a society started by a group of industrialists, businessmen and professionals for promoting professional / technical education, has started functioning from academic year 1995-1996 with a permission of AICTE and affiliated to JNTU.

The Department of Electronics and Communication Engineering has decided to conduct programs for the benefit of teaching and Industry professional.

The Department of Electronics and Communication Engineering offering B.Tech in ECE and M.Tech in VLSI System Design and Embedded Systems. The Department with 28 faculty members has well equipped labs in the field of Communication, Microprocessors, Micro controllers, the VLSI System Design Lab including Digital, Analog and Mixed Signal and DSP processors Lab.

VNR VJIET is the first local chapter of VLSI Society of India, since January 28, 2006.

Registration Fees:

Faculty and Students

Rs. 1500/-

Industrial Participants

Rs. 6000/-

The course fee should be sent to the coordinators by Demand Draft in favour of

“VSI chapter VNRVJIET“, payable at Hyderabad along with the registration Form.

Important:

Last Date for receiving applications: 20 August2006

Selected Candidates will be informed by 23-08-2006

Note: The Number of participants is limited to 30.

For Details Contact:

M. Srinivasa Rao

9866696151

srmudunuru@yahoo.com

N. Balaji

9848115663

narayanamb@rediffmail.com

Venue: (Refer the location plan)

The VNR Vignana Jyothi Institute of Engineering and Technology is located near

Bachupally Village, Ranga Reddy District, about 8 km. from Miyapur junction along the

inner ring road. From JNTU College of Engineering, Kukatpally is about 6km. Via

Pragathi Nagar. Participants can avail College Bus Facility free of charge.

Bus Timings:

From Koti at 8.00A.M, reaching the institute at 9.20 a.m Via Lakdi-ka-pool,

Ameerpet, ESI, Erragaddda, Kukatpally, JNTUC and Miyapur Junction.

From Secunderabad at 8.10A.M, reaching the Institute at 9.20A.M. Via

Secunderabad Railway Station (Reservation Complex), Bowenpally, Balanagar,

Kukatpally, KBHB, JNTUC and Pragathi Nagar.

Download announcement (pdf)

Location Plan

For the convenience of the students, arrangements have been made with the A.P.State Road Transport Corporation to run more than 10 exclusive buses to the Institute from Kukatpally as per the following timings
	Kukatpally to Campus	Campus to Kukatpally
Five buses	9:00 to 9:15 AM	4:00 PM
Five buses	9:15 to 9:30 AM	4:00 PM *
^* Out of the 5 buses, one leaves the campus at 5:00PM also, for the convenience of the students who want to utilize the Library and Sports facilities in the Campus. ^* Out of the 10 exclusive buses, two buses are being run as LADIES SPECIALS.

*Short Term Intensive Course on* DFT for Digital Design 4^th–6^th September 2006** VNR Vignana Jyothi Institute of Engineering and Technology, Hyderabad www.vnrvjiet.ac.in Download announcement (pdf)
Sponsored by: VLSI Society of India vlsi-india.org/vsi “To contribute and promote the advancement of all aspects of VLSI technology, primarily in India” Organized by Dept of ECE, VNR-VJIET, Hyderabad www.vnrvjiet.ac.in “To develop as an institute of excellence to train human resources to international standards in the areas of Engineering and Technology”	Co-ordinators:
	Prof. C.D. Naidu HOD Dept of ECE	M. Srinivasa Rao Associate Professor Dept of ECE				N.Balaji Associate Professor Dept of ECE
	Course Resource persons: C.P. Ravikumar, Senior Technologist, Texas Instruments, India Ram Jonnavithula, Project Manager, DFT, Texas Instruments, India Jais Abraham, Head-Technology, InnoDes Solutions Pvt. Ltd. Course Contents: What is VLSI Testing and why is required? Test Process, different types of test, ATE Economics of Testing and concepts of Yield Fault models and Combinational Testing ATPG - D algorithm Podem Fault Simulation Sequential Testing Time-frame expansion technique Testability - controllability and observability Motivation for DFT - Scan-based test Boundary Scan Delay Testing Reliability Testing - IDDQ and Burn-in Memory Testing Built-in Self-Test Logic BIST and Test Compression Design for Test - area and performance considerations System-level Testing. Hands-on experience on Mentor EDA Tools DFT Advisor Fast Scan Course Duration: 4 - 6 September 2006. Target audience: Faculty Members from Engineering Colleges, students and professionals from the Industry.



The “Valluripalli Nageswara Rao (VNR) Vignana Jyothi Institute of Engineering and Techonology” Sponsored by “VIGNANA JOTHI”, a society started by a group of industrialists, businessmen and professionals for promoting professional / technical education, has started functioning from academic year 1995-1996 with a permission of AICTE and affiliated to JNTU. The Department of Electronics and Communication Engineering has decided to conduct programs for the benefit of teaching and Industry professional. The Department of Electronics and Communication Engineering offering B.Tech in ECE and M.Tech in VLSI System Design and Embedded Systems. The Department with 28 faculty members has well equipped labs in the field of Communication, Microprocessors, Micro controllers, the VLSI System Design Lab including Digital, Analog and Mixed Signal and DSP processors Lab. VNR VJIET is the first local chapter of VLSI Society of India, since January 28, 2006.
	Registration Fees:
	Faculty and Students			Rs. 1500/-
	Industrial Participants			Rs. 6000/-
	The course fee should be sent to the coordinators by Demand Draft in favour of “VSI chapter VNRVJIET“, payable at Hyderabad along with the registration Form.
	Important: Last Date for receiving applications: 20 August2006 Selected Candidates will be informed by 23-08-2006 Note: The Number of participants is limited to 30. For Details Contact:
	M. Srinivasa Rao		9866696151		srmudunuru@yahoo.com
	N. Balaji		9848115663		narayanamb@rediffmail.com
	Venue: (Refer the location plan) The VNR Vignana Jyothi Institute of Engineering and Technology is located near Bachupally Village, Ranga Reddy District, about 8 km. from Miyapur junction along the inner ring road. From JNTU College of Engineering, Kukatpally is about 6km. Via Pragathi Nagar. Participants can avail College Bus Facility free of charge. Bus Timings: From Koti at 8.00A.M, reaching the institute at 9.20 a.m Via Lakdi-ka-pool, Ameerpet, ESI, Erragaddda, Kukatpally, JNTUC and Miyapur Junction. From Secunderabad at 8.10A.M, reaching the Institute at 9.20A.M. Via Secunderabad Railway Station (Reservation Complex), Bowenpally, Balanagar, Kukatpally, KBHB, JNTUC and Pragathi Nagar.