Course details ... Registration form
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Organized by
VLSI Society of India In cooperation
with
C-DAC Hyderabad and
IEEE TTTC
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3-day Short Course on Design for Testability – Theory and Practice July 27-29, 2006Hyderabad
Venue:
Hotel Fortune Katriya (www.fortunekatriya.com) Instructors: Prof. Adit Singh and Prof. Vishwani Agrawal, Auburn University |
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Overview: The three-day course on
“Design for Testability” is intended for practicing engineers as well as
faculty and students. It will provide an overview of the subject by two
leading experts in the field, who will sprinkle the contents with recent
developments in the area. |
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 Vishwani D. Agrawal is James J. Danaher Professor of Electrical & Computer Engineering at Auburn University, Auburn, Alabama, USA. He has over thirty years of industry and university experience, working at Bell Labs, Rutgers University, TRW, IIT in Delhi, EG&G, and ATI. His areas of research include VLSI testing, low-power design, and microwave antennas. He has published over 250 papers, holds thirteen U.S. patents and has co-authored 5 books including Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits with Michael Bushnell at Rutgers. He is the founder and Editor-in-Chief of the Journal of Electronic Testing: Theory and Applications, was a past Editor-in-Chief of the IEEE Design & Test of Computers magazine, and is the Founder and Consulting Editor of the Frontiers in Electronic Testing Book Series. Dr. Agrawal is a co-founder of the International Conference on VLSI Design, and the International Workshops on VLSI Design and Test, held annually in India. He served on the Board of Governors of the IEEE Computer Society in 1989 and 1990, and, in 1994, chaired the Fellow Selection Committee of that Society. He has received seven Best Paper Awards, the Harry H. Goode Memorial Award of the IEEE Computer Society, and the Distinguished Alumnus Award of the University of Illinois at Urbana-Champaign. Dr. Agrawal is a Fellow of the IETE-India, a Fellow of the IEEE and a Fellow of the ACM. He has served on the advisory boards of the ECE Departments at University of Illinois, New Jersey Institute of Technology, and the City College of the City University of New York. |
 Adit D. Singh is James B. Davis Professor of Electrical & Computer Engineering at Auburn University, where he directs the VLSI Design & Test Laboratory. Earlier he has held faculty positions at the University of Massachusetts in Amherst, and Virginia Tech in Blacksburg. His research interests are in VLSI design, test, and reliability, and he has published extensively in these areas. Over the years he has taught approximately 50 short courses in-house for companies including IBM, National Semiconductor, TI, AMD, Bell Labs and Sandia Labs (earlier also for Digital, Control Data, and Data General), and at IEEE technical meetings, and through university extension programs. These have primarily been in the areas of VLSI design, test, reliability and fault tolerance. Prof. Singh currently serves on the Executive Committee of the IEEE Test Technology Technical Council, on the Editorial Board of IEEE Design and Test, and is the General Chair of the 2003 IEEE Memory Test Workshop. He is a Fellow of IEEE and a Golden Core Member of the IEEE Computer Society. |
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Course contents |
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The exponential nature
of the testing problem Fault models Stuck-at faults Test generation for
combinational circuits D algorithm PODEM, FAN and learning
based ATPG Fault coverage Fault simulation Fault grading Testability measures Test generation
algorithms for sequential circuits Scan and partial scan
design Functional testing of
microprocessor/controllers Design for testability |
Built in self-test
(BIST) Test compression
techniques for test data volume reduction Boundary scan and the
IEEE 1149 testability standard Memory testing Memory BIST SOC test issues P1500 core test standard Current testing: IDDQ
and IDDT Structural delay testing Fmax and MinVDD testing Test cost and effective
ness Test coverage and defect
levels Stress testing Reliability Screens for burn -in minimization |
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