Design for Testability – Theory and Practice

A Three-day Intensive Course

December 15 – 17, 2005, New Delhi, India (Venue To be Announced)

 

Organized by VLSI Society of India

http://vlsi-india.org/vsi/

In cooperation with:

IEEE Circuits and Systems Society

     

http://www.ieee.org

VSI Home   VSI Events

 

Schedule:

Registration on Day-1 at 8.30 AM

Course on all days begins at 9.00 AM

Lecture 1

Introduction

Lecture 2

Yield and Quality

Lecture 3

Fault Modeling and Exercise-1

Lecture 4a

Logic Simulation

Lecture 4b

Fault Simulation

Lecture 5

Testability Measures

Lecture 6

Combinational ATPG and Exercise-2

Lecture 7

Sequential ATPG and Exercise-3

Lecture 8

Memory Test

Lecture 9

Analog Test

Lecture 10

DFT and Scan and Exercise-4

Lecture 11

BIST

Lecture 12

System Diagnosis

Lecture 13

Test compression techniques

Lecture 14

At-speed testing techniques for SoC

Lecture 15

Signal integrity issues in Test (about 1.5 hrs)

Lecture 16

Power issues in Test

 

Instructors:

Vishwani Agrawal (Auburn University) and

C.P. Ravikumar (Texas Instruments, India)

 

Dr. Vishwani D. Agrawal is James J. Danaher Professor of Electrical &Computer Engineering at Auburn University, Auburn, Alabama, USA. He has over thirty years of industry and university experience, working at Bell Labs, Rutgers University, TRW, IIT in Delhi, EG&G, and ATI. His areas of research include VLSI testing, low-power design, and microwave antennas. He has published over 250 papers, holds thirteen U.S. patents and has co-authored 5 books including Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits with Michael Bushnell at Rutgers. He is the founder and Editor-in-Chief of the Journal of Electronic Testing: Theory and Applications, was a past Editor-in-Chief of the IEEE Design & Test of Computers magazine, and is the Founder Editor of the Frontiers in Electronic Testing Book Series.

Dr. Agrawal is a co-founder of the International Conference on VLSI Design, and the International Workshops on VLSI Design and Test, held annually in India. He served on the Board of Governors of the IEEE Computer Society in 1989 and 1990,and, in 1994, chaired the Fellow Selection Committee of that Society. He has received seven Best Paper Awards, the Harry H. Goode Memorial Award of the IEEE Computer Society, and the Distinguished Alumnus Award of the University of Illinois at Urbana-Champaign. Dr. Agrawal is a Fellow of the IETE-India, a Fellow of the IEEE and a Fellow of the ACM. He has served on the advisory boards of the ECE Departments at University of Illinois, New Jersey Institute of Technology, and the City College of the City University of New York.

Dr. C.P. Ravikumar is with Texas Instruments India as a Senior Technologist in VLSI Test. Before joining TI, he served on the faculty of the Department of Electrical Engineering at IIT Delhi as a Professor. He has published over 150 papers in international conferences and journals. He has served as the technical program chair for VLSI Design Conference and the VLSI Design and Test Symposium. He has also served as the member of the program committee for several conferences, including HiPC. He is the recipient of SIGDA student scholarship award, best paper award (VLSI Design conference) and best student paper award (VLSI Design conference). He is a senior member of IEEE, Fellow of the Indian Microelectronics Society, and current secretary of VSI.

 

Registration:

To download the registration form, please click on the link below:

The course fee will be charged, as indicated in the table below:

Course Fee

Before November 1, 2005

After November 1, 2005

Industry Members (Non- Members)

Rs. 9,000/-

Industry Members (Non-Members)

Rs. 10,000/-

VSI/ IEEE members

Rs. 7,500/-

VSI/ IEEE members

Rs. 8,500/-

Academic/governmental organizations from India (Non-members)

Rs. 6,000/-

Academic/governmental organizations from India (Non-members)

Rs. 7,000/-

Academic/governmental organizations from India (Members of VSI/ IEEE)

Rs. 4,500/-

Academic/governmental organizations from India (Members of VSI/ IEEE)

Rs. 5,500/-