Workshop on VLSI Physical Design Automation

December 19-21, 2005 Hotel Atria Bangalore India
Organized by

In cooperation with

http://vlsi-india.org/

VLSI Society of India

 

 

http://www.ieee.org

IEEE Circuits and Systems Society, Bangalore Chapter


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Overview: VLSI Design is experiencing tremendous growth due to advances in technology and scaling in feature sizes.  As designers are given greater ability to pack more logic in a VLSI chip, the process of generating layouts is also becoming increasingly complex. CAD tools have to deliver effective solutions for vastly scaled up problems and in the presence of very stringent constraints. A designer must understand the problems associated with the design as well as the workings of CAD tools to arrive at early design closure.

This short course is primarily designed for introducing the physical design automation of VLSI systems. Thus, primary focus is on the algorithms for designing tools. However, each topic also deals with the complexity of design and thus provides opportunities for designers for preparing to tackle large complex designs. Design automation related issues for the current state of the art will set the theme and introduce problems in existing techniques in VLSI design. Data structures and algorithms related to design automation will provide insight into design of CAD tools.

The course will provide understanding and relationships between design automation algorithms and various constraints posed by VLSI fabrication and design technology. Critical performance related parameters and their importance in design automation tools would be introduced.

 

Instructor:

Dinesh Bhatia is member of faculty of electrical engineering at The University of Texas at Dallas. He is also program head for computer engineering at UT-D. He directs research activities within the Embedded and Adaptive Computing group and is also a member of Center for Integrated Circuits and Systems at the University of Texas at Dallas.

He received a Bachelor's in Electrical Engineering from Regional Engineering College, Suratkal, India, and a MS and a Ph.D. in Computer Science from the University of Texas at Dallas. His research interests include all aspects of reconfigurable and adaptive computing, architecture and CAD for field programmable gate arrays (FPGAs), physical design automation of VLSI Systems, power aware programmable architectures, network on chip solutions for SoCs and, computer engineering education.

He has extensive experience in building large scale embedded and reconfigurable systems. Some of these activities include principal designer and investigator for RACE and NEBULA systems for Wright Laboratories of USAF, principal investigator for DARPA funded REACT program, Co-PI on AFRL funded SPARCs program and several more. He has collaborated on phase 1 and phase 2 SBIR programs to build product prototypes.

He has published extensively in leading journals and conferences and continues to serve on program committees of several conferences. He is a senior member of IEEE, Computer Society, Circuits and Systems Society, Eta Kappa Nu, and recently served on the editorial board of IEEE Transactions on COMPUTERs.

Course Syllabus:

Integrated Circuit Design Related

1

Introduction:

Technology, trends, and complexity of design.

4

Interconnection Problem

·          Interconnect delay and modeling

·          Interconnection Synthesis

·          Clock and Power

·          Emerging Paradigms

  

2

Fundamental Algorithmics

·          Basic data structures

·          Problem representation and formulations

·          Fundamental algorithms

  

 

 

o         Network on Chip

o         2.5D and 3D design/packaging

 

 

o         Floorplanning

o         Placement

o         Routing

o         Managing complexity and dealing with scaling

o         Challenges

5

A roadmap for future designs

·          Heterogeneous Designs

·          Adaptable Architectures

·          Designing in the presence of faults

  

3

Modern Layout Generation Techniques

·          Interconnect Planning

·          Front end tool interaction

Target Audience:

This short course is intended for many parties. Anyone who is interested in VLSI design and CAD should take this class. Those people who wish to pursue research and/or career in the field of VLSI CAD must take this course. VLSI engineers who wish to become better designers by clearly understanding the complexities of design, tools, and problems will benefit from this course. Finally, tool users will be exposed to intricacies behind the tool design and will gain better understanding for proper tool usage.

  

 

o         Estimation

o         Floorplanning

  

·          Placement for very large circuits

·          Timing Driven Routing

  

 

Course Fee

Before November 15, 2005
After November 15, 2005

Professionals (Non- Members)

Rs. 6,000/-

Professionals (Non- Members)

Rs. 7,000/-

Professionals (VSI/ IEEE members)

Rs. 5,000/-

Professionals (VSI/ IEEE members)

Rs. 6,000/-

Students/Faculty  (Non-members)

Rs. 3,000/-

Students/Faculty  (Non-members)

Rs. 3,500/-

Students/Faculty  (Members of VSI/ IEEE)

Rs. 2,500/-

Students/Faculty  (Members of VSI/ IEEE)

Rs. 3,000/-

 

Do download the registration form, please click here: