Designing a modern System-on- Chip for Test – An industrial perspective

Designing a modern System-on- Chip for Test – An industrial perspective A one-day workshop March 9, 2007 Venue: Conference Room, CEP Building, DA-IICT Near Indroda Circle, Gandhinagar - 382 007, Gujarat, India

Sponsors Texas Instruments India http://www.ti.com VLSI Society of India http://vlsi-india.org/vsi/ DA-IICT Ahmedabad http://www.daiict.ac.in/	A one-day workshop is planned at DA-IICT, Ahmedabad on March 9, 2007 on the topic of “Designing a modern system-on-chip for Test – An Industrial Perspective”. Objective The objective of the workshop is to provide an exposure of modern-day DFT practices to the participants. Audience The workshop will be appropriate for faculty, PG students, and final-year undergraduate students with interest in microelectronics. Speakers The workshop will be conducted by Dr. C.P. Ravikumar and Mr. Ram Jonnavithula of Texas Instruments India, Bangalore. Topics Introduction to “Design for Test” Fault models for logic and memory Low-cost Test practices At-speed Testing Impact of variability on Test
Registration	The workshop is open to faculty, PG students, and final-year undergraduate students. Those who wish to register for the workshop must contact Prof. D. Nagchoudhuri of DA-IICT no later than March 1, 2007. Registration would be on a first-come first serve basis. Limited seats are available constrained by infrastructural resources.
Charges	There will be no charges, though admission would be on the basis of prior registration only. All participants would be required to make their own arrangements for board and lodging. The DA-IICT does have a cafeteria on the premises for use of their students and faculty. On prior request, permission to use the cafeteria may be provided.
Contact	For registration, all candidates may email Prof. D. Nagchoudhury of DA-IICT: dnc@daiict.ac.in with the subject line "Registration for System-on-Chip Testing". They must indicate their name, organization and address in the mail. Specific request for cafeteria facility must be included. No requests for board and/or lodging would be entertained.
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Technical Program
09.30 AM – 10.30 AM	Registration
10.30 AM – 11.30 AM	Introduction to DFT; Fault models for logic and memory
11.30 AM – 11.45 AM	Tea break
11.45 AM – 01.00 PM	Low-cost Test Practices; At-speed Testing
01.00 PM – 02.00 PM	Lunch break
02.00 PM – 03.00 PM	Impact of Variability on Test
03.00 PM – 03.15 PM	Tea break
03.15 PM – 04.00 PM	Industrial Practices