2^nd Workshop on Mixed-Signal VLSI Design and Test

DAY - 1

Keynote Talk

Why does Low Voltage not imply Low Power In Analog VLSI?

Dr Shanthi Pavan obtained the B.Tech degree in Electronics and Communication Engg from the Indian Institute of Technology, Madras in 1995 and the M.S and Sc.D degrees from Columbia University, New York in 1997 and 1999 respectively. From 1997 to 2000, he was with Texas Instruments in Warren, New Jersey, where he worked on high-speed analog filters and data converters. From 2000 to June 2002, he worked on microwave ICs for data communication at Bigbear Networks in Sunnyvale, California. Since July 2002, he has been with the Electrical Engineering Department of the Indian Institute of Technology-Madras, where he is an Assistant Professor. His research interests are in the areas of high-speed analog circuit design and signal processing.

Abstract: Progressive scaling of power supply voltages have resulted in digital ICs with reduced power consumption. This talk is intended to be a tutorial treatment of what low voltage operation means to the analog designer, why lower voltages do not necessarily imply a lower power dissipation in analog circuits.  Practical examples in the areas of active filters and data converters will be given as illustrations.

Design and Evaluation of A/D converters

Asif Ahmad completed M.Tech. from Electrical department of IIT Delhi in dec.1997 and B.Tech from AMU (Aligarh) in Jun1996. He joined Data Converter group of Texas Instruments, Bangalore. After working in TI for 3.5 years, he joined ADI in Aug 2001. Presently he is Project Manager with ASC group of ADI, Bangalore. His area of interest is A/D converters. He has designed several high speed 12/14 bit serial SAR ADCs in small packages.  He has one Patent and 5 papers on SAR ADC in different conferences.

Abstract: Analog to Digital converters are one of the most important component of signal processing chain. Innovations in circuit designs, manufacturing and IC fabrications, and packaging has helped A/D converter designers to come up with novel ideas to achieve high speed, and high resolution A/Ds. At the same time better understanding of system or signal processing chain or end applications has helped designers to design application specific A/Ds which is optimized in power, cost, speed and resolution. Once designed, it becomes really important to evaluate the high performance A/Ds to its maximum limits.

In this talk I will try to give an overview of commonly used A/Ds (SAR, Pipeline and Sigma Delta, with more emphasis on SAR) with some insight of new architectures (time interleaved architecture). In overview I will touch upon all the important parameters taken care during design (SAR as example). I will spend some time on evaluation of A/Ds commonly faced problems and suggested workaround.

Analog Test in an SoC Device

Arjun Prakash graduated from EEE Department, MSRIT Bangalore in 2004 and has been working as a Test Engineer with Tessolve for 3 years. He has been working on Analog testing for about 2 1/2 years and his work mainly involves testing of power management and AFE sub-systems. He plays a lot of computer games, plays drums and dreams about traveling every part of the world someday.

Sheetal Morajkar obtained BE in Instrumentation Engg from VIT Pune and Diploma Instrumentation Engg from Mumbai. She has 3Years+ experience in silicon validation and characterization (TI). Also experienced in broadband, cable modem, RF power-Amp IC’s. 2.5 years in automation products electronic modular design and testing (Honeywell).

Abstract: A system-on-chip (SoC) device integrates digital logic cores such as microprocessors and digital signal processors, memories, and analog circuit blocks. In this presentation, we examine the aspects of testing the typical analog blocks, namely, power management circuits, analog filters, and data converters.  Since battery energy conservation and minimizing the peak power are important in today’s power-hungry SoC, on-chip power management blocks are included for supplying power to the entire chip.  We will consider tests such as line regulation, load regulation, no-load voltage and load-voltage tests for testing the power-management blocks.   Analog filters are used for removing undesirable signals such as spikes and noise signals.  We will examine tests for measuring the 3-dB point, pass-band gain, and stop-band attenuation for the filters. Data converters are necessary for conversion of analog signals from the sensors into digital format for the digital signal processor, and vice versa.  We shall examine tests such as linearity tests, signal-to-noise ratio (SNR) tests, and total harmonic distortion (THD) tests.

Analysis and Design of CMOS Subcircuits

Dr. R. Neelaveni is presently working as an Assistant Professor in the Department of Electrical Engineering of PSG College of Technology, Coimbatore. She has 19 years of teaching exprience. Her area of interests includes Biomedical Instrumentation, Soft Computing and Analog VLSI. She has been handling these subjects for the past 2 years and is very much interested in the design of CMOS circuits. She has published about 16 papers in Journals, International Conferences and National Conferences.

Abstract: The operational amplifier is one of the versatile and important building block of analog circuit design. It is the best example of how simple circuits are connected to perform a complex function. This lecture will focus on the design and analysis of sub circuits namely, Current Sources/ Sinks, Current Mirrors, Voltage and current references at the first level of design and amplifiers at the second level.

Applications of Genetic Algorithms to Design of Operational Amplifiers

Dr. M.C. Bhuvaneswari received her B.E. from Government College of Technology and M.E. and Ph.D. from PSG College of Technology. She has about 18 years of teaching experience. Presently she is Assistant Professor, in the Department of Electrical and Electronics Engineering, PSG College of Technology. She has published about 20 technical papers at conferences and Journals and her research interests include VLSI Testing, Genetic Algorithms and Digital System Design.

Abstract: Genetic algorithms has been employed in many computer aided design (CAD) problems for digital circuit optimization. This search technique can be successfully applied to a class of optimization problems in which the search space is too large to be sampled by conventional methods. This presentation studies the problem of CMOS operational amplifier design optimization and how genetic algorithms can be applied to this multi-objective optimization problem. Simulation results of GA applied to synthesis of a standard Miller OTA cell will be presented.

DAY - 2

A tutorial on Analog VLSI Filters

Switched Capacitor and Operational Transconductance Capacitor Filters

Dr. P.V. Anand Mohan obtained Ph.D from I.I.Sc, Bangalore in 1975. Since 1973 till 2003, he was with ITI Limited, Bangalore in R&D. Since 2004, he is with ECIL, Bangalore as Executive Dirctor. Dr. Ananda Mohan has published extensively in the area of Analog filters, Residue Number systems and VLSI architectures. He has published three books --one in the area of Switched Capacitor filters (Prentice-Hall, London), one on Current-mode VLSI analog Filters (Birkhauser, Boston), and one on Residue Number systems (Kluwer Academic Publishers). He has been elected a Fellow of IEEE in 2005 and is a Fellow of IETE. He has received the Ram Lal Wadhwa Gold medal of IETE and Indira Priyadarshini Award. He was past Associate Editor of IEEE Transactions on CAS Part I and presently is the Associate Editor of Jour CSSP, Birkhauser and IETE Journal of Research. He is a reviewer for Electronics Letters, IEE Journals and IEEE Transactions. He also is a specialist in cryptography.

Abstract: The subject of Analog Filter design for MOS VLSI is considered in detail. The concept of SC filters is introduced to together with an idea of biquad implementations, practical issues such s area and spread, sensitivity, ladder filters etc. Application to realize over-sampled A/D converters is also considered. The design of OTA-C filters using the device OTA is also considered. The various issues such as need for tuning, programmability etc are considered. A brief introduction to current-mode VLSI analog filters using devices such as Current conveyors, CFOA etc., is also discussed.

Design Planning for Mixed Signal SoCs

Jairam Sukumar is a Member Group Technical Staff at Texas Instruments India. He received his BS in Electrical Engineering from Dayalbagh, Agra and Masters in Electronics Design from Indian Institute of Science, Bangalore in 1998 and 2000 respectively. Since then he has been with the SoC Center of Excellence, Texas Instruments, Bangalore. He worked on Physical Design of Mixed Signal SoCs for Broadband Applications. His current focus is on development of methodologies for Electrical and Reliability analyses for SoCs. He is also working towards his PhD in the area of SoC design methods for MEMS at Indian Institute of Science, Bangalore. His fields of interest include CAD Algorithms, optimization problems for Physical Design and CAD for MEMS.

Abstract: Mixed Signal SoCs require extensive planning for integration of highly sensitive analog IPs along with high performance digital blocks. This talk reviews basics of noise generation and its propagation. It provides an overview of the design planning methodology and analysis methods for such scenarios.

Some Research Issues in Digital-to-Analog Converters

Dr. Chetan D.Parikh obtained his B.Tech. Degree from the Indian Institute of Technology (IIT), Bombay, in 1985, and his M.S. and Ph.D. degrees from the University of Florida, Gainesville, in 1988 and 1992, respectively, all in electrical engineering. From 1994 to 2000, he was on the faculty of IIT-Bombay. He was a Visiting Associate Professor at the University of Missouri - Rolla (2000 - 2001), and at Purdue University (2001 - 2002). Then he worked at Motorola, Inc. in Austin, Texas (2003 - 2004). Since July 2004, he has been an Associate Professor at the Dhirubhai Ambani Institute of Information and Communication Technology (DA-IICT), Gandhinagar. Dr. Parikh’s research interests are in the design of analog and mixed-signal circuits. He has had sponsored and consultancy projects from government agencies (DST, DOE), as well as industries (TI, National Semiconductors, GE). He has more than 30 publications in international journals, and conferences.

Abstract: This talk will:

1. Provide a very brief introduction to major digital-to-analog converter (DAC) architectures, followed by
2. An overview of current research, and challenges, in high-speed DAC architectures with particular emphasis on current-steering DACs.

Methods to minimize glitches, SFDR, systematic and random errors in DACs will be discussed.

Test Challenges in the Nanometer Era

Jais Abraham graduated from the Indian Institute of Technology at Chennai, India. Prior to his current role as the Director - R&D, InnoDes Solutions, he has had 8 years of experience in DFT at Texas Instruments (India) where he was a Member, Group Technical Staff. During this time, he worked on complex designs ranging from CPU’s with custom datapaths to multi-million gate SOCs. He was actively involved in initiating many DFT technologies at TI-India including scan compression and multi-site testing for test cost reduction. He has also worked with EDA vendors to enhance/add key DFT features in their tools. He has co-authored several papers in National and International conferences holds 6 patents in the area of DFT.

Abstract: The shrinking geometries and the increasing levels of integration in Nanometer technologies has resulted in several challenges for test, which were hitherto not considered significant. Engineers and researchers need to understand these issues and brace themselves up to face them.

This talk focuses on a few of the important problems in Nanometer test and describes the solutions to these problems. The talk will conclude by giving an economic justification for solving these problems.

Mixed Signal Verification – Idea to Implementation

 Girish Vaidya completed M.Tech. from Centre for Electronics Design and Technology, Indian Institute of Science in Jan 2003 and BE from Government College of Engineering Pune in June 2001.Since then he has been with Wipro Technologies Bangalore. He started his career with system design group. Later he moved into the Analog-Mixed signal chip design group, taking up the responsibility of developing AMS verification as an independent practice. In the present role, he is leading the analog and mixed-signal verification activity at Wipro Technologies. His current focus includes evolving the flow and methodology with emphasis on reusability and automation.

Abstract: As the interface between the analog and digital parts within a chip continues to become more complex, the need for independent mixed signal verification is gaining importance.

There are various approaches being followed for mixed signal chip verification, ranging from independent analog-digital verification to usage of behavioral models and co-simulation tools. Even the tools used for mixed signal chip verification take different approaches, each approach having a distinct flavour. Behavioral modeling, with its pros and cons offers another dimension to the mixed signal verification space.

The talk would discuss about the need, approaches and challenges in the mixed signal verification domain considering some real case studies.

How to Accelerate Mixed-Signal Verification using Fast-SPICE?

 Anil Bhatnagar received his M.Tech. in Computer Science & Engineering from I.I.T. Bombay in 1992 and M.Sc.(Tech.) Computer Science from B.I.T.S. Pilani in 1990. He is currently working as a Member of Consulting Staff in the Custom IC division of Cadence Design Systems in Noida, contributing to the development of Analog/ Mixed-Signal Design Environments.

Abstract: The total mixed signal market is growing and today mixed signal constitutes 65% of chip design work. Half of the respins occur mainly due to issues in mixed signal during the design phase. SPICE simulations were mostly used for mixed signal verification. However, SPICE simulations, though accurate, are time consuming and can often run for several days. Fast-SPICE simulators can help in increasing overall productivity by speeding up simulations considerably. This presentation focuses on how to speed up mixed signal verification using Fast-SPICE simulation. High level features of Fast-SPICE simulators will be covered to list out how Fast-SPICE can be leveraged for mixed signal verifications.

Please also register using the online registration form at http://vlsi-india.org/vsi/activities/reg.shtml apart from sending the filled hardcopy of registration form, and to notify spot-registration. Download Announcement with Registration Form. PDF 250KB