Two-day Course on Low-power Design and Test

UPDATED : 28 June 2007
Course details ... Program Schedule

Two-day Course on Low-power Design and Test
July 30-31, 2007, Hyderabad
Greenlands, Begumpet, Hyderabad, Tel: 091 - 040 - 66515151, 23757575, Green Park - Hyderabad

Duration: Two days. 9.00 AM to 5.30 PM

Registration on Day-1	8.30 AM – 9.00 AM
Course on all days	9.00 AM – 5.30 PM

Target Audience: The course is relevant to chip designers, low power EDA tool developers,
academics and researchers working in the area of VLSI design.

Schedule:

Day 1	09.00 – 10:30AM	Introduction	Vishwani Agrawal
	10:30 – 11.00AM	Coffee break
	11.00 – 12:30PM	Dynamic and static power in CMOS	Vishwani Agrawal
	12:30 – 02.00PM	Lunch
	02.00 – 03:30PM	Logic-level power estimation	Srivaths Ravi
	03:30 – 04.00PM	Coffee break
	04.00 – 05:30PM	High-level power estimation	Srivaths Ravi

Day 2	09.00 – 10:30AM	Architectural techniques: State machines, bus encoding	Vishwani Agrawal
	10:30 – 11.00AM	Coffee break
	11.00 – 12:30PM	Memory, multicore design	Vishwani Agrawal
	12:30 – 02.00PM	Lunch
	02.00 – 03:30PM	High-level design methods Power management techniques	Srivaths Ravi
	03:30 – 04.00PM	Coffee break
	04.00 – 05:30PM	Test power	Srivaths Ravi

Download announcement with registration form PDF 110KB

Registration on Day-1

8.30 AM – 9.00 AM

Course on all days

9.00 AM – 5.30 PM